HDL to schematic presentation

[aizenr]

Is there a software that transforms an HDL file into a graphic schematic presentation of the chip?

Thank you very much,
Rmai

[WBahn]

There are some tools that do that for mainline HDLs like VHDL or Verilog, but I strongly doubt anyone has ever tried to do something like that for this HDL, which is a toy HDL developed by the authors for this set of projects.

But look at the bright side -- I've never seen automatically generated schematics that are worth the match it would take to turn them to ashes, so you aren't missing out on much.

[aizenr]

Thank you very much.

Could you please direct me to tools that make it to VHDL. I think it will be rather easy for me to make a translator from HDL to VHDL (I guess, I do not know VHDL yet, but since HDL is so simple, how bad can it be...).

The reason that I'm interested in it is that I think that it will be satisfactory for my kids to see their own design in a schematic presentation that looks like something that can be actually turned into a computer.

Thanks again,
Rami

[ashort]

I highly recommend Logicly (available online, or as a native Mac or Windows app).  It's really easy to use, easy enough for kids, and a lot of fun. You have to manually lay out the logic gates yourself, but honestly, most HDL files are so simple that it's trivial to hand-design them in Logicly.   In fact, I recommend the opposite approach: design first in Logicly where you can graphically see if you have the logic right (light bulbs light up!), then hand-write in HDL when you know it works.

Once you have a chip designed in Logicly, you can package it as a chip and re-use it in other chips.

I actually used Logicly to design the entire Hack computer (see my other post: logicly).  It was tedious, but I did it, and I'm glad I did, because I learned a lot of nuances I never would have learned otherwise.  

But even if you don't design the entire computer, certainly using it for the beginning sets of chips would be enormously useful.

[WBahn]

Writing a converter to go from the Hack HDL to either Verilog or VHDL is pretty straightforward, largely because the Hack HDL is so simple and, even more so, because it is purely structural (no behavioral).

The tools I used back when I was doing HDL design work were usually vendor-specific (for instance, Xilinx or Altera) and most of them had this feature. It was usually used to let people design a schematic using a schematic capture program and then generate a structural HDL file from it. That's very easy to do -- it's just a netlister, really. But they also had the ability to go the other way in order to document designs. Like most autoplace tools for printed circuit boards, what they really did was give you a starting place that at least had all the parts and connections on it, but you spent quite a bit of effort moving things around to get them to be presentable (or even comprehensible).

Fortunately, the number of distinct parts in the Hack library and the number of parts in a given HDL file are small enough that this would actually be a reasonably efficient approach.

Another way you could approach it would be to look at the definitions (or reverse engineer them) for some of the more basic schematic capture files and take this same approach -- just create a file that places the parts at random locations and defines the nets that connect them. Then open the resulting file in that editor and manually massage it to look nice and presentable. If you use an editor that has decent rubberband editing support, that will make it go much more smoothly.

[pranavji]

Hi. I developed this vs code extension which can visualize hdl files.

Here is a link: https://marketplace.visualstudio.com/items?itemName=PranavJain.nand2tetris-hdl-visualizer&ssr=false#overview 

Thanks