Hdl file doesnt load

[LAW]

/**
 * Not gate:
 * out = not in
 */

CHIP Not {
    IN in;
    OUT out;

    PARTS:
   Not(IN=in, OUT=notin);
}
 
Fails to load on the hardware simulator even though it's encoded in ANSI. Help will be appreciated.

[cadet1620]

You should see in the status message at the bottom of the Hardware Simulator is stuck loading Not.hdl.  This is a bug in the simulator that it hangs instead of giving a real error message.


What's happening is that your Not chip encounters the "Not(...)" in the Parts section and loads your Not.hdl, which sees the Not(...), which loads.......

When you are building your Not.hdl, the only part that you have available is Nand. You need to figure out how to connect the a and b inputs of a Nand gate to get it to generated Not. (Hint: the only thing that they can be connected to are 'in', 'true' and 'false'.)

Once you have built and tested your Not, then you can use Nand and Not to build And.

--Mark