Albert G wrote

Like the book says, there are many ways to implement all of the gates, especially so for the more complex ones. Some of the solutions are more efficient than others: maybe they use less wires ? Or they use a smaller number of parts ? Or the smallest number of internal pins ?

"Optimization" is tough to define; it's a many-faceted problem. What parameters do you optimize for: speed, number of components, power used, cost, reliability, ...? For TECS, there are three obvious metrics that could be optimized: Nand gate count, number of HDL hdl part lines, worst case Nand gate delay count.

What's the best gate to count? That depends on the type of logic family (IC process) being used. For some it's Nand, for others its Nor. For CMOS, both have equal speed but Nors are physically larger. For some families, extra inputs on the basic gate cost almost nothing so you would count a 1-input Nand (Not) the same as an 8-input Nand.

Since one of the major goals for this course is to teach abstraction, minimizing HDL code might be a good metric to optimize, but it leads to some rather convoluted circuits. Consider this Mux:

Xor(a=a, b=b, out=x); // (If you turn this in for your Mux,

And(a=x, b=sel, out=y); // your teacher will ask you how it

Xor(a=a, b=y, out=out); // works!)

It's cute; I don't think it can be done in fewer lines of HDL. But as a real-world solution its gate count is high, it's slow, and it's full of hazard glitches.

This is too complex an issue to try to address in an entry level course. Do some Google image searches, for instance "4-input multiplexer circuit", and you'll see examples of real world implementations.

--Mark