Mux4Way16 implementation

[cweiss]

I'm thinking of building a Mux4Way then build the Mux4Way16 from that. Would that be efficient?
To build a Mux4Way should a, b, c, and d get muxed in a bracket system (a with b, c with d, then the out of those two get muxed) or is there a simpler way?

[cadet1620]

cweiss wrote

I'm thinking of building a Mux4Way then build the Mux4Way16 from that. Would that be efficient?
To build a Mux4Way should a, b, c, and d get muxed in a bracket system (a with b, c with d, then the out of those two get muxed) or is there a simpler way?

More efficient from a less typing point of view is to use the Mux16 you already have to make Mux4Way16. Takes 3 lines of HDL.

--Mark

[mike]

I see the mux16 is relatively easy, but when I want to make it complicated (just for fun!) and try to write it with the mux function there is a problem. If I try :

mux(a=a[0], b=[0], sel= sel[whatever], out = ab[0])

the simulator say I 'can not subindex internal variables' (or similar). Is there any way to solve this without falling back to a 16bit chip first?
Thanks
Mike

[ybakos]

out is a one-bit output. You can't magically create a bus and attach one wire to the 0th element of the bus. In other words, out = ab[0] is not valid.

[Mike]

Thanks for the fast answer, but if I get it right you are saying there is no way to write Mux4Way16 with NAND only?
Well I exclude the option of creating 16 unique variables (ab0, ab1, ab2 ..._)
Thanks
Mike

[cadet1620]

Mike wrote

Well I exclude the option of creating 16 unique variables (ab0, ab1, ab2 ..._)

That's what you need to do if you want to use 1-bit wide parts to build something wider. When I did the Nand ALU I wrote an HDL preprocessor that made this simpler.  It takes a line like
    Nand(a=x[#], b=x[#], out=notX#);
and replicates it 16 times replacing # with 0 through 15.

--Mark

[Mike]

WOW!
Thanks
Mike

[superRyan]

I need help,sir
by using Mux16 to implement the Mux4way16 chip,i figure out this construction:

but this will cause an internal bus problem
one of my HDL code is:
Mux16(a=a[0..15], b=b[0..15], sel=s1, out[0..15]=o1[0..15]);

syntax problem in out[0..15]=o1[0..15]

by the way, why is Hack HDL not able to assign internal buses?
i think it will be more convenient for readers to implement complex chip with internal buses.

[ybakos]

Your hdl can be simplified, and you can indeed wire internal buses - just not using the [0..15] syntax.

If an input to one chip is 16 bits, there is no need to use the subscript syntax [0..15] to wire an exsiting 16-bit bus to the input. For example:

Mux16(a=a, b=b, sel=s1, out=o1);

o1 is a 16-bit internal pin that you can now wire as the input to another chip's 16-bit input.

[superRyan]

thank you so much!
it's very helpful.