Mux4Way16

[hdllearn]

Hi All,
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/1/Mux4Way16.hdl
/**
 * 4-way 16-bit multiplexor:
 * out = a if sel = 00
 *       b if sel = 01
 *       c if sel = 10
 *       d if sel = 11
 */

 CHIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];
   
    PARTS:
    ////And, Or, Not, Xor, Mux, Mux16, And16, Or16, Not16
    //// Replace this comment with your code.
   
    Not(in=sel[0], out=notsela);
    Not(in=sel[1], out=notselb);


    ////if sel[0] = sel[1], out=out1. i.e (a=0 and b=0) or (a=1 and b=1) out = 1 or 0
    //sel=00 or sel=11
    And(a=sel[0], b=sel[0], out= outand1);

    //00. outand7=0
    And(a=sel[1], b=sel[0], out=outand7);
    Not(in=outand7, out=notoutand7);
    And(a=notoutand7, b=notoutand7, out=out00);

    //10. outand8=1
    And(a=outand7, b=sel[1], out=outand8);
   
    ////sel=01 or sel=10
    //Good
    And(a=sel[0], b=sel[1], out=outxor1);
   
    ///sel=01
    ///And(a=outxor1, b=notselb, out=out10);
    Or(a=outxor1, b=notselb, out=out10);
    ////sel=11
    Or(a=outxor1, b=notsela, out=out11);
   

    //outa, outb, outc, outd are all good
    //sel=00
    Mux16(a=a, b=b, sel=outand7, out=outa);
    //sel=10
    Mux16(a=c, b=d, sel=outand8, out=outc);
    //sel=01
    Mux16(a=a, b=b, sel=out10, out=outb);
    //sel=11
    Mux16(a=c, b=d, sel=out11, out=outd);

    //Algo"
    //gates we have: And, And16, Or, Or16, Or8way, Not, Not16, Mux, Mux16, DMux, Nand
    //NB:Or will bitwise Or for 16 bits of 2, 16 bits.
    //We need a SWITCH to switch between a[16], b[16], c[16], d[16]
    //Therefore cannot use And16, Or16
       
    //a or b or c or d
    //Or8Way(in[0]=outand7, in[1]=outand8, in[2]=out10, in[3]=out11, out= interout);
    Or8Way(in[0]=outand7, in[1]=out11, out=interaord);
    //And(a=interout, b=outand7, )



    //Mux16(a=outa, b=outd, sel=outand7, out=finala);
    //Mux16(a=outb, b=outc, sel=out10, out=finalb);



}

I need help to select the final outpput for 'out=out'.

Please help!

Thanks

[WBahn]

The first thing that caught my eye was this:

And(a=sel[0], b=sel[0], out= outand1);

What purpose is this supposed to serve?

Describe your intended approach.

One way to visualize things is that you have a cereal dispenser that has four funnels at the top being fed with different cereals. At the bottom you have a single output to dump the chosen cereal into a bowl. You have two lights on the wall that will tell you which of the four funnels should be routed to the bowl. You can use in your construction a bunch of valves the each have to input pipes and one output pipe and a switch that chooses which input pipe is connected to which output pipe.

Draw a picture of how you could connect up the valves so that, based just on the two lights, you can set the switches on the valves so that the desired cereal is sent to the bowl.

[hdllearn]

the purpose of
 //sel=00 or sel=11
  And(a=sel[0], b=sel[0], out= outand1);

is to determine if sel[0] =sel[1] or not

[WBahn]

hdllearn wrote

the purpose of
 //sel=00 or sel=11
  And(a=sel[0], b=sel[0], out= outand1);

is to determine if sel[0] =sel[1] or not

And how is it supposed to do that?

If sel[0] = 0, what is outand1 going to be?

If sel[0] = 1, what is outand1 going to be?

What does sel[1] have to do with it?

Be sure to look at what you actually wrote, not what you meant to write.

[hdllearn]

Hi WBahn

that is what I am doing,

choosing between
sel[2]=00
sel[2]=01
sel[2]=10
sel[2]=11

so my logic is find out if the sel[2] = 00 or sel[2] is 11
then differentiate between these 00 and 11

My problem is when I have determine which selector it is i.e. 00, 01, 10 or 11 I output a, or b or c or d.

But once I get the ouptu I do not know how to set out = out.

[hdllearn]

Hi WBahn

how do I switch between 'outa', 'outb', 'outc' or 'outd???'

[hdllearn]

Hi WBahn
outa, outb, outc and outd

are at the bottom of the file/codes

[WBahn]

There is no sel[2] signal. The sel signal is two bits. The signal name sel refers to the complete two-bit bus, while sel[0] refers to one signal in it and sel[1] refers to the other. The signal sel[2] only exists if the bus has at least three bits in it.

Where you see sel[2] used is in this line:

IN a[16], b[16], c[16], d[16], sel[2];

In the IN and OUT lines, the number in square brackets is just telling the simulator how many bits are in the signal.

Be that as it may, how does the line I asked you about do anything?

  And(a=sel[0], b=sel[0], out= outand1);

Again, look at what is actually there, not what you want to be there.

What signal is connected to the 'a' input of that And gate?

What signal is connected to the 'b' input of that And gate?

How does Anding those two signals help accomplish what you want?

[WBahn]

hdllearn wrote

Hi WBahn

how do I switch between 'outa', 'outb', 'outc' or 'outd???'

Do you not already have a part that can select between two 16-bit inputs?

Look back to the suggestion I made about making a cereal dispensing machine using valves that, by themselves, only let you choose between two input pipes to send to one output pipe.

[hdllearn]

My logic is:
choose 00 or 11 t are similar since sel[0] = sel[1].
Then differentiate if the sel[0]=0 or 1

[WBahn]

You are refusing to read what you actually wrote in your code.

Look at the following line of code as if some stranger provided it and claimed that it did something based on the values of both sel[0] and sel[1]. Would you agree with them that it does that?

  And(a=sel[0], b=sel[0], out= outand1);

Again, look at what is actually there. Answer the following questions for the line directly above here. Don't answer it based on what you think is should be, answer it based on what is actually there.

What signal is connected to the 'a' input of THAT And gate?

What signal is connected to the 'b' input of THAT And gate?

How does the output signal outand1 depend, in any way, on sel[1], based on THAT And gate?

[hdllearn]

Hi WBahn

thanks for you bearing with me.

I am a novice and I know my logic may not be adequate.

I am thinking of your question you last sent me:
And(a=sel[0], b=sel[0], out=out1);

Thanks for your patience with me

[WBahn]

That's fine. We'll get there.

Let's make the issue easier to see by replacing sel[0] with x and sel[1] with y.

That makes it

And(a=x, b=x, out=out1);

while claiming that it somehow is doing something based on the relationship between x and y.

Do you see the problem?

[hdllearn]

I think I partially understand. I don't use outand1 anywhere again in the code.

[WBahn]

Then why is it there?

It just gets in the way of discussing your logic. The person reading your code assumes that it represents your logic, but if it is littered with abandoned code fragments, it makes it very hard to discern what that logic is, because they spend time chasing deadends.

It also makes it easy for you to end up chasing deadends.

So the best thing at this point is probably for you to take a few minutes to clean up your code, something that should be done periodically, anyway, so that we have a more focused starting point for our discussion.

At the same time that you are doing that, try to replace signal names such as 'out7' with names that convey the information carried by that signal. That will make it a LOT easier for everyone, yourself included, to understand the logic behind your code.

[hdllearn]

This piece of code:
And(a=sel[0], b=sel[0], out=out1);

is useless. I don't use it for anything after that.

[WBahn]

So get rid of it -- it just causes confusion.

[hdllearn]

HIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];
   
    PARTS:
    ////And, Or, Not, Xor, Mux, Mux16, And16, Or16, Not16
    //// Replace this comment with your code.
   
    Not(in=sel[0], out=notsela);
    Not(in=sel[1], out=notselb);


    //00. outand7=0
    And(a=sel[1], b=sel[0], out=outand7);
    Not(in=outand7, out=notoutand7);
    And(a=notoutand7, b=notoutand7, out=out00);

    //10. outand8=1
    And(a=outand7, b=sel[1], out=outand8);
   
    ////sel=01 or sel=10
    //Good
    And(a=sel[0], b=sel[1], out=outxor1);
   
    ///sel=01
    ///And(a=outxor1, b=notselb, out=out10);
    Or(a=outxor1, b=notselb, out=out10);
    ////sel=11
    Or(a=outxor1, b=notsela, out=out11);
   

    //outa, outb, outc, outd are all good
    //sel=00
    Mux16(a=a, b=b, sel=outand7, out=outa);
    //sel=10
    Mux16(a=c, b=d, sel=outand8, out=outc);
    //sel=01
    Mux16(a=a, b=b, sel=out10, out=outb);
    //sel=11
    Mux16(a=c, b=d, sel=out11, out=outd);

    //Algo"
    //gates we have: And, And16, Or, Or16, Or8way, Not, Not16, Mux, Mux16, DMux, Nand
    //NB:Or will bitwise Or for 16 bits of 2, 16 bits.
    //We need a SWITCH to switch between a[16], b[16], c[16], d[16]
    //Therefore cannot use And16, Or16
       
    //a or b or c or d
    //Or8Way(in[0]=outand7, in[1]=outand8, in[2]=out10, in[3]=out11, out= interout);
    Or8Way(in[0]=outand7, in[1]=out11, out=interaord);
    //And(a=interout, b=outand7, )



    //Mux16(a=outa, b=outd, sel=outand7, out=finala);
    //Mux16(a=outb, b=outc, sel=out10, out=finalb);



}

[WBahn]

Let's look at the following code segment:

    //00. outand7=0
    And(a=sel[1], b=sel[0], out=outand7);
    Not(in=outand7, out=notoutand7);
    And(a=notoutand7, b=notoutand7, out=out00);

I'm inferring that the intent is for out00 to be 1 exactly when sel = 00. Is that correct?

If so, that means that you do NOT want it to be 1 for any of the other three possible values of sel, correct?

So make a truth table and walk through your logic -- again, the logic AS written, not as intended -- and figure out what out00 will be for all four possibilities for sel.

[hdllearn]

yes you are right. out00 is 1 for 00, 01 and 10 also.