Nand is not found?!

[FourKings]

Help!

I am now trying to run my "And.hdl" but a error message comes up: "Nand is not found in the working or buildin folders ".

I just build a Not.hdl which summons the Nand as well and theres no problem at all! Plz help!

I use Microsoft word to edit hdl. Here is my statement:

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
　　Nand(a=a, b=b, out=v);
[Remainder of source code removed by admin.]
}

The error message occurs when I try to load the And.hdl

[cadet1620]

The source code that you posted has Unicode characters in it. The Nand2Tetris tools don't support Unicode. Make sure that you save your files with ANSI or MSDOS encoding, not UTF-*.

It's easier to use a text editor, not a word processor. A nice, free, text editor for Windows is Notepad++.

Please edit your post to remove the working source code.

--Mark

[FourKings]

Hi Mark,

Thx for ur last replay! That really solved my problem!

Now I have another one and it bothered me a lot.

I build the gates from not to mux already, but, the problem is, I build some of them just by trying random combinations of gates that I already have. I dont know how to work out the desired logic base on the given truth table.

What did I miss? Please help!


--Sean

[cadet1620]

FourKings wrote

I build the gates from not to mux already, but, the problem is, I build some of them just by trying random combinations of gates that I already have. I dont know how to work out the desired logic base on the given truth table.

What did I miss? Please help!

The simple circuits, up through the Mux and DMux, can be designed algorithmically from their truth tables using the "canonical" form as described in chapter 1. The canonical form can often be simplified using Boolean algebra or Karnaugh maps. See this post for more info on K-maps.

When you made your Or, you probably discovered one aspect of De Morgan's Law. it's useful to know in all of its forms.

Canonical form becomes unmanageably complex when more than 5 or 6 inputs are involved.

The 4- and 8-way Muxes and DMuxes can be designed starting with canonical form, but this is harder than designing them using abstraction: think of the N-way Muxes as making a series of choices and build that series of choices using the Mux to make the individual choices. This is analogous to building the Or8Way using a series of Or gates.

Try to get into the mindset that every part you build becomes another tool that you can use to build even more complex parts.

--Mark

[FourKings]

Thanks, Mark! Thats exactly what Im looking for!

However, here's another question:

I just done building DMux4Way chip and this is my output
in sel a b c d
0 00 0 0 0 0
0 01 0 0 0 0
0 10 0 0 0 0
0 11 0 0 0 0
1 00 1 0 0 0
1 01 0 0 1 0
1 10 0 1 0 0
1 11 0 0 0 1

As you can see i have a comparison failure at line 6 and 7.

Here is the header of my chip:
CHIP DMux4Way {
    IN in, sel[2];
    OUT a, b, c, d;
PARTS:
//
}

It turns out that I have a misunderstanding of of how values of sel are assigned to sel[0] and sel[1],

As the above table suggested in line 6,  in=1, sel=01, does it mean sel[0]=0, sel[1]=1?

Thank you very much for your patience and time!

[cadet1620]

Hardware bus bits are numbered from RIGHT to LEFT. This is so that when the bus is carrying a binary number, bus[N] is the wire carrying the 2^N bit.

When sel=01, sel[0]=1 and sel[1] = 0.

--Mark