New to Chapter 1

[johnny5]

Hi,

I recently began to go through the intro and chapter 1. I am having difficulty in understanding how to create the simple AND gate using NAND.  This seems like it should be very basic however I can't seem to come up with the correct HDL syntax. Are there any hints you would be able to offer? I've read through most of the relevant posts on this forum as well and trying to gather info other places.  I feel as though if I'm unable to complete these simple inital task on my own, it may not be the right time for me to try the course.

Thanks

[cadet1620]

johnny5 wrote

Hi,

I recently began to go through the intro and chapter 1. I am having difficulty in understanding how to create the simple AND gate using NAND.  This seems like it should be very basic however I can't seem to come up with the correct HDL syntax. Are there any hints you would be able to offer? I've read through most of the relevant posts on this forum as well and trying to gather info other places.  I feel as though if I'm unable to complete these simple inital task on my own, it may not be the right time for me to try the course.

Thanks

There are two questions here. First is how to logically create And from Nand. The definition of Nand is
    Nand (a, b) = Not (And (a, b))
and Not is its own inverse
    Not (Not (a)) = a.
Combine these two ideas to make And.

For syntax examples of HDL see Figures 1.6 and A.1. The important thing to know is the the name on the left side of '=' in the parts lines is always an I/O pin in the part being used and the right side is always a pin or wire in the part being designed. Thus, a Nand part will always be coded
    Nand (a=something, b=something, out=something);
You know that the Nand part's I/O pins are a, b and out from looking at the specification in the gray box in 1.2.1.

Also note that is is very important to implement and test the chips in the order listed in 1.3 since later chips depend on your having written the earlier ones.

--Mark

[johnny5]

Mark,

Thanks for your response. I'm still not grasping what I need to do.  I keep reading this as programming variables although I understand I shouldn't. Is Not allowed in the HDL, or is it strictly Nand we're supposed to use?

---

Date: Tue, 30 Oct 2012 02:27:53 -0700
From: [hidden email]
To: [hidden email]
Subject: Re: New to Chapter 1

johnny5 wrote

Hi,

I recently began to go through the intro and chapter 1. I am having difficulty in understanding how to create the simple AND gate using NAND.  This seems like it should be very basic however I can't seem to come up with the correct HDL syntax. Are there any hints you would be able to offer? I've read through most of the relevant posts on this forum as well and trying to gather info other places.  I feel as though if I'm unable to complete these simple inital task on my own, it may not be the right time for me to try the course.

Thanks

There are two questions here. First is how to logically create And from Nand. The definition of Nand is
    Nand (a, b) = Not (And (a, b))
and Not is its own inverse
    Not (Not (a)) = a.
Combine these two ideas to make And.

For syntax examples of HDL see Figures 1.6 and A.1. The important thing to know is the the name on the left side of '=' in the parts lines is always an I/O pin in the part being used and the right side is always a pin or wire in the part being designed. Thus, a Nand part will always be coded
    Nand (a=something, b=something, out=something);
You know that the Nand part's I/O pins are a, b and out from looking at the specification in the gray box in 1.2.1.

Also note that is is very important to implement and test the chips in the order listed in 1.3 since later chips depend on your having written the earlier ones.

--Mark

---

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[johnny5]

I now see that Not should be built before And. I'm not sure why I decided to try And first.  I'll keep banging away at this with Not first and will respond if I get stuck again. (hopefully not)

Thanks

---

Date: Tue, 30 Oct 2012 02:27:53 -0700
From: [hidden email]
To: [hidden email]
Subject: Re: New to Chapter 1

johnny5 wrote

Hi,

I recently began to go through the intro and chapter 1. I am having difficulty in understanding how to create the simple AND gate using NAND.  This seems like it should be very basic however I can't seem to come up with the correct HDL syntax. Are there any hints you would be able to offer? I've read through most of the relevant posts on this forum as well and trying to gather info other places.  I feel as though if I'm unable to complete these simple inital task on my own, it may not be the right time for me to try the course.

Thanks

There are two questions here. First is how to logically create And from Nand. The definition of Nand is
    Nand (a, b) = Not (And (a, b))
and Not is its own inverse
    Not (Not (a)) = a.
Combine these two ideas to make And.

For syntax examples of HDL see Figures 1.6 and A.1. The important thing to know is the the name on the left side of '=' in the parts lines is always an I/O pin in the part being used and the right side is always a pin or wire in the part being designed. Thus, a Nand part will always be coded
    Nand (a=something, b=something, out=something);
You know that the Nand part's I/O pins are a, b and out from looking at the specification in the gray box in 1.2.1.

Also note that is is very important to implement and test the chips in the order listed in 1.3 since later chips depend on your having written the earlier ones.

--Mark

---

If you reply to this email, your message will be added to the discussion below:

http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/New-to-Chapter-1-tp4025492p4025493.html

To unsubscribe from New to Chapter 1, click here.
NAML