Nor gate

[Matt Keenan]

I realise that in hardware Nor gates aren't used as much as Nand gates. Although I only have passing knowledge of electrical engineering my impression for the reason for less use of Nor gates was that the slew rate of a p gate was quicker in parallel on a rising signal and the slew rate for a n gate was quicker on a falling signal; hence Nand gates are quicker than Nor gates. Having said that there are times when using a Nor gate is justified as it might save from using a more complex gate structure than using just Nands and Nots and hence have a faster overall slew rate for the whole. On that basis is it possible to get a Nor gate added as a builtin? In furtherance of this, I have added a repo to github for this simple patch;

https://github.com/mattkeenan/nand2tetris.git

[cadet1620]

This slight speed advantage of Nand over Nor only applies to CMOS, where it's easy to make both Nand and Nor. 30+ years ago when I was learning all this, the most prevalent logic was TTL which only had N-input Nand as its primitive gate, and if you needed very high speed you used ECL which only had Nor. Who knows what the world will look like 30 years from now.

For the purpose of the Nand2Tetris course, I think that adding a Nor built-in as an alternate primitive gate would just add confusion. In my Hack Computer there are only two instances where I have an Or followed by Not, so I also don't think that it's justified to add Nor to the list of Project 1 synthesized gates.

Real world hardware implementation is also not a concern of this course. For instance, nobody implements Xor on an IC using Nand/Nor; nor would they implement Or8Way using a tree of 2-input Ors.

If you haven't already found it, you sound like you might enjoy Logisim, a schematic based logic simulator that's powerful enough to build a hack-like computer.

--Mark

[Matt Keenan]

I agree that the topic is indeed too large to dive into on a whim, but I figured it would be easy enough to add the primitive. I am somewhat aware of the optimisation tricks like 6 transistor Xor gates and multiway gates using either 2n or 2n+2 transistors. You could easily design a CPU with predominately Nor gates rather than Nand, my point is you should explain the preference for Nand over Nor even if it is a one sentence hand wave; then it provides a student with an easy gateway to further learning if they chose to go further down the rabbit hole.

[WBahn]

Apologies for reviving a long-dead thread, but some might find these observations useful.

I, too, lament the lack of a 2-input NOR gate (even if it were implemented via NAND gates to keep with the basic premise of NAND to Tetris) because there are simplications that could be made to subsequent logic if it were part of the tool kit. It would also let me talk more naturally about how these circuits, in general, are really implemented. Instead, I emphasize that the notion of building everything from NAND gates isn't to show how anything actually IS done, but merely to show how it conceptually could be done. To back this up I do some comparisons between transistor counts on the NAND-based circuits built here and the counts on real designs of the same circuits.

I think we need to keep in mind the amazingly ambitious scope of the material and acknowledge that the quid-pro-quo for cramming it all into a remarkably coherent one-semester project is that anything that isn't essential pretty much isn't there. I actually use the lack of a 2-input NOR gate to underscore this point.

Pedagogically, I would rather see the project include the implementation of the DFF using combinatorial gates -- so that it truly does become NAND to Tetris -- but I realize that the simulator simply isn't up to dealing with fundamental mode machines. So I supplement the material showing them this design and walking through how it works. I also show them how NAND, NOT, and NOR gates are implemented in CMOS. I doubt few other instructors do, which is perfectly fine.

Speaking as someone that spent well over a decade designing full-custom CMOS ASICS, while it is true that a 2-input NAND is faster than a comparably-sized 2-input NOR, this is almost never a major consideration. In particular, if you need a NOR function, you would never implement it using a NAND with inverters on all of the inputs and outputs -- talk about cutting your nose off to spite your face! In the vast majority of circumstances you just use a 4-transistor NOR gate having the same sized transistors as your NAND gate (which in turn has the same size transistors as your NOT gate). This is because this makes it easier to pack all of the gates in a design into an overall smaller area of the die and this usually trumps performance in most designs because your basic logic speed is so much faster than you actually need.

For those designs were speed is an issue, you put in the effort to size the transistors to get balanced speeds and, in designs that are pushing the speed limits of the technology, you go to topologies that pretty much double the transistor count in order to use more of a current-steering approach to get high speed and low noise.

As for things like 6-transistor XOR gates, they have their place (usually where silicon area is the dominant driving factor and you can tolerate pretty poor performance). In most other designs, the fact that the output is not isolated from the input is a major, even disqualifying, disadvantage.

All of these, and so much more, are great side discussions to have but I don't think they should be part of the ECS text. Keep it clean and let the other courses that delve into the various topics in depth deal with these.