Not gate

[jonzzzsat]

I have done the reading on the first task, and I am working the hardware simulator well enough to test repetitively, but I can't seem to crack the not gate? I am a self learner. can someone give me some hints?

I repeatedly get comparison error in line two and three. My understanding is the output must match the compare, for the chip to be right. I don't know where to go from the compare (I notice it in the truth table), to working out where my implementation is wrong. I get different outputs, but I don't know how or why? to fix it.
   

[WBahn]

Take the truth table for a Nand gate:

a b out
0 0  1
0 1  1
1 0  1
1 1  0

For a Not you only use one of the inputs. So the question is what can you do with the other input so that the input/output relationship is correct for a Not gate?

[jonzzzsat]

What can I do with the other input, if it is not fed it will default to 0. I tried running (a=false,out=out), but I still get my comparison errors. I run (a=in,b=in,out=out) and I get comparison errors - line 2 and 3. -IN THE OUTPUT FILE I GET THE TRUTH TABLE FOR A NOT CHIP, BUT THIS IS STILL A COMPARISON ERROR LINE 2 AND 3? I tried (a=in,a=in,out=out) and I followed the in and out readings; this observation is the closest I have got to a Nand truth table. In it I perceive the problem is input b its not dragging to input a which I think it should. I am at a loss as to what to do with input b so it will combine with input a? I consider if the solution is with the Nand chip itself, or something to do with the feed. I don't know?    

[WBahn]

Why do you think that an unconnected input will default to 0? Does it state that somewhere? It might, but I don't recall it saying that.

Regardless, don't leave inputs unconnected. Even if a simulator does what you would like it to do in that case, the real world is seldom as accommodating.

Tying both inputs together should work fine. I would need to see your actual code to tell better whether there is anything wrong there. Also, are you sure you haven't modified either the test script or the comparison file in any way? They are a matched set. You might recopy them from the original download (or download them fresh).

Post the contents of your output and compare files (say the first five lines). That may shed some light.

You might also consider what the behavior of a Nand gate is if one input is tied HI (true).

[jonzzzsat]

I downloaded the file again and it solved the problem. I have completed the test successfully, I am still a computer learner I must have altered something. But in respect to the most efficient implementation the ideas I generated in my folly got me thinking about it nonetheless. Now I recall the most efficient chip is the one with the fewest parts. So in respect to the not chip - one Nand must be the most efficient? If I found another way that passed the test does the Simulator install the most efficient? How does it decide? But like you said, to connect all pins nonetheless. Is the compare file that is generated on testing - the interface chip truth table? It says unconnected output pins will default to 0 in the HDL survival guide under unconnected pins. Now this might be a silly question but I feel like playing around with the Hardware Simulator, but once I have implemented a chip it stores it in memory and I move on to the next at will?    

[WBahn]

jonzzzsat wrote

I downloaded the file again and it solved the problem. I have completed the test successfully, I am still a computer learner I must have altered something.

Glad that solved the problem. It's easy to accidentally change a file, so I keep a virgin download in a different directory that I can always pull clean copies from.

But in respect to the most efficient implementation the ideas I generated in my folly got me thinking about it nonetheless. Now I recall the most efficient chip is the one with the fewest parts.

Not necessarily. Also, it depends on what metric is being used to judge efficiency.

 So in respect to the not chip - one Nand must be the most efficient?

Actually, no. In terms of the building blocks you have to work with, it's the best you can do. But in the real world you would prefer to use an actual Not gate. In CMOS, a Not gate consists of two transistors while a Nand gate consists of four.

If I found another way that passed the test does the Simulator install the most efficient? How does it decide?

The simulator simply uses whichever one you provide to it. If you don't have an implementation in the directory at all, then it uses its internal model which is nothing more than a Java function that implements the desired logic and has no concept of digital gates being connected.
 

But like you said, to connect all pins nonetheless. Is the compare file that is generated on testing - the interface chip truth table? It says unconnected output pins will default to 0 in the HDL survival guide under unconnected pins.

The HDL survival guide is not definitive and was not written by the authors. I've found a couple of errors in it. I don't know if Cadet1620 (who wrote it) looked at the source code to determine how unconnected pins are handled. I do know that the simulator behaves somewhat erratically with signals that are generated by not used.

Now this might be a silly question but I feel like playing around with the Hardware Simulator, but once I have implemented a chip it stores it in memory and I move on to the next at will?

It doesn't store implemented chips in memory. Every time you run the simulator it looks for the chip implementations in the working directory and, if it finds them, it uses them. Otherwise it uses the internal Java model.