Not test failing

[Andreas]

Hi,

I wrote the following HDL code for the Part section of the Not.hdl chip:

Nand(a=in, b=true, out=c);

However this seems to fail the test, and I don't see why.

If in=0, then a=0 and b=1. 0 AND 1 is 0, negating this makes 1, therefore c=1.
If in=1, then a=1 and b=1. 1 AND 1 is 1, negating this makes 0, therefore c=0.

Sorry if I have missed something extremely obvious...it is quite late here.

Thanks for any help.

[cadet1620]

This is a bit of a trap in the HDL language.  The output of the Nand gate is connected to internal wire "c" which goes nowhere.  You have not connected anything to the "out" output of the Not chip.  There are no error messages or warnings associated with this type of problem.

--Mark

[Andreas]

Ah thank you! I thought the compiler wouldn't be able to handle the ambiguity so I didn't try it.