On the implementation of the ALU without Multiplex

[Naff]

I'd like to know if there would be a real performance difference if the blocks before the adder/And16 didn't use multiplexors. if x was one of the inputs to a And16, and the other input being !zx, if zx is 0, then x is passed through unchanged. If zx is 1, all of the Ands come out as 0. A similar thing seems feasible using Xor (though there is no Xor16 chip included in the files) to invert the result of And16.

[cadet1620]

The multiplexor is a nice efficient circuit, consisting of only 4 Nand gates. The worst case delay is through the select input and is 3 gate delays:

    

x ~zx implemented in Nands is also 3 gate delays.

Adding an inverter to the B input to handle nx does not change the Mux's worst case delay since this inverter is in parallel, timing wise, with the inverter on SEL.

Xor also takes 3 Nand gate delays, so the circuit speed is also the same for both solutions to handle nx.

--Mark

[cadet1620]

In real world hardware, it's easy to make N-input gates that have the same propagation delay as 2-input gates, so the Nand implementation of Mux4Way look like this.

    

One again, the inversion of x fits in nicely in parallel with the inverters on s0 and s1 lines so that using a 4-way mux is twice as fast as the And-Xor idea.

--Mark