|
|
|
|
I just discovered this feature by trying it. It's a feature in VS Code and other modern code editors.
When you're doing the long list of gates to build a Not16 from sixteen Not gates, for example,
you can first copy one Not line, and then copy/ paste to create sixteen of them
Not(in=in[0], out=out[0]);
Not(in=in[0], out=out[0]);
Not(in=in[0], out=out[0]);
Not(in=in[0], out=out[0]);
and so on..
Then go to the second line where the index values should be 1's
Place the cursor after the first zero,
and then hold down the Alt key and click after the second zero on that line,
the editor will show two blinking cursors, one at the end of each zero.
Now if yoiu press the backspace key once and then type a '1' it'll replace all three 0's
with 1's.
More generally, whatever you type happens all all the current multi-cursor locations,
so if you sent a cursor someplace and then hold down the Alt key, then any place you click
will add more cursors.
It would be better if the HDL language supporte some kind of FOR loop but the multi-cursor
at least makes editing the lines a bit quicker.
Dave
|
|
Administrator
|
DaveAZ wrote
It would be better if the HDL language supporte some kind of FOR loop but the multi-cursor
at least makes editing the lines a bit quicker.
Any kind of a loop is largely incompatible with an HDL, whose purpose is to describe the hardware topology. Many HDL languages support such constructs, but they are largely there to enable the development of test benches and not the description of the hardware. Supporting being synthesizable to actual hardware is a very nontrivial undertaking that simply isn't worth the effort for an extremely narrow and short-term project like N2T.
|
|
|
I agree that some kind of general purpose for loop function isn't needed. I was just describing one possible shorthand notation to more concisely describe, for example, a 16 bit inverter constructed from 16 single-bit inverters. Is there a way, perhaps I've missed, to do that in HDL, i.e. without having to list the 16 1-bit inverters explicitly?
Thanks,
Dave
|
|
Administrator
|
Certainly not in this HDL and not in most HDLs or schematic capture packages (and an HDL is primarily a way to encode a schematic). While I'm sure there are others, I've only used one schematic capture package that had good features for instantiating iterated instances of parts. I can't quite remember the name of the package, but it allowed the creation of very complex systems using just a few parts provided the connections between them had a very regular pattern. For instance, you could make a ripple-carry adder (like the one in the Hack) with a single Full-Adder component.
But, while powerful, it also made for very cryptic schematics that had to be carefully analyzed to understand and were even more fiendishly difficult to debug. So I suspect that having a comparable feature in this HDL would end up being counterproductive and would actually make it more difficult for people at this stage of learning to implement things and be successful.
Plus, while the value of having this ability seems high, it really isn't for this project. If you aren't struggling with figuring out the logic associated with the part you are designing, the actual writing of the HDL to implement them takes very little time. For instance, implementing the And16 from opening the virgin seed file to saving the final result ready for testing takes well under a minute and a half. Once you have the And16, you can leverage it to create the Or16 in under thirty seconds (without even using the find-and-replace features of most text editors).
In fact, you can start from scratch and implement everything in Chapters 1, 2, 3, and 5 in under an hour and a half. So, it would likely take longer to learn how to use the more powerful description features than using them would actually save. If this HDL were going to be what they used for projects beyond N2T, it would make more sense (though there are other features that I would put a much higher value on, such as cleaner sub-busing or pass-through connections), but people that continue with any HDL will probably transition very quickly to Verilog or VHDL.
As limited as it it, the N2T HDL is probably at about the right level for students learning these concepts as it forces them to match the implementation of the HDL code very closely to the conceptual logic of the parts they are implementing.
|
|
Administrator
|
DaveAZ wrote
I agree that some kind of general purpose for loop function isn't needed. I was just describing one possible shorthand notation to more concisely describe, for example, a 16 bit inverter constructed from 16 single-bit inverters. Is there a way, perhaps I've missed, to do that in HDL, i.e. without having to list the 16 1-bit inverters explicitly?
Another point to keep in mind is that you can built up wide parts exponentially very easily (and this is key to implementing the large memory arrays in Chapter 3).
For instance, you don't have to implement a Not16 using sixteen Not gates. Instead, you could build a Not2 using two Not gates, followed by a Not4 using two Not2 gates, then a Not8 using two Not4 gates, and finally a Not16 using two Not8 gates. You can trade off depth for width, too. For instance, implement a Not4 using four Not gates followed immediately by a Not16 using four Not4 gates.
|
|
Locked
