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They give you an example in Fig 1.6, where they show you one way to implement an Xor gate.
You just want to do the same thing for your Not gate, with the limitation that all you can use are Nand gates.
I would recommend doing what they are doing in that Figure. First, draw out the schematic of how you would use interconnect the parts you are using and how they would connect to the pins of the part you are making. Then label each wire with a name. Wires connected to pins have to use the pin name, but wires that are just interconnecting parts internally can use any name you want -- but they have to have a name.
The HDL code itself is nothing but saying which wire each pin on each part is connected to. It's no more complicated than that.
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