Project 3 PC.hdl

[john.shimin.zhang]

Apologies if this has already been mentioned, the comment for PC.hdl states:
/**
 * A 16-bit counter with increment, load, and reset modes.
 * if      (inc(t))   out(t+1) = out(t) + 1
 * else if (load(t))  out(t+1) = in(t)
 * else if (reset(t)) out(t+1) = 0
 * else               out(t+1) = out(t)
 *
 * To select a mode, assert the relevant control bit,
 * and de-assert the other two bits.
 */
which implies that inc overrides load, which overrides reset. In the test script, the expected behavior is actually
/**
 * A 16-bit counter with increment, load, and reset modes.
 * if      (reset(t))   out(t+1) = out(t) + 1
 * else if (load(t))  out(t+1) = in(t)
 * else if (inc(t)) out(t+1) = 0
 * else               out(t+1) = out(t)
 *
 * To select a mode, assert the relevant control bit,
 * and de-assert the other two bits.
 */
That is, reset overrides load, which overrides inc

[WBahn]

See this discussion here.

It's good that you are paying such close attention.