Project 5: Order sensitivity in HDL?

classic Classic list List threaded Threaded
1 message Options
Reply | Threaded
Open this post in threaded view

Project 5: Order sensitivity in HDL?

Since this is (potentially) a bug report, I hope it is OK to post solutions here for Project 5.

When running my code for the Computer chip in the Web IDE, the following solution passed all the required tests:
CHIP Computer {

    IN reset;

    ROM32K(address= pc, out= instruction);    
    Memory(in= outM, load= writeM, address= addressM, out= inM);
    CPU(inM= inM, instruction= instruction, reset= reset, outM= outM, writeM= writeM, addressM= addressM, pc= pc);

However, switching the order of the Memory and CPU makes the tests fail. I'd just like to confirm that this is in fact a bug, possibly related to that described here