Question about constants in HDL

[mpthompson]

I did a bit of Verilog work a few years back and when specifying inputs to a gate, one could simply specify a 0 or 1 -- they are effectively a true/false constant.  Is something similar possible in Nand2Tetris style of HDL?  For instance, could one specify the AND gate as:

IN a, b;
OUT out;
Nand(a=a, b=b, out=nout);
Nand(a=nout, b=1, out=out);

Notice the 'b' input on the second Nand is simply tied to 1.

[mpthompson]

Hate to answer my own question, but the trick to using true/false constants in HDL is to use the "true" or "false" keywords.  Duh...

IN a, b;
OUT out;
Nand(a=a, b=b, out=nout);
Nand(a=nout, b=true, out=out);

I'll try to sleep on a question before asking it next time.