RAM64 address allocation problem within DMux and Mux

classic Classic list List threaded Threaded
9 messages Options
Reply | Threaded
Open this post in threaded view
|

RAM64 address allocation problem within DMux and Mux

ajksdf
When I come across the exercise of RAM64, I am thinking of these 3 problems but I still don't know what the correct answers. Any thoughts are welcome. Thank you very much.

1. Why do DMux and Mux need to use the same bit of address while those 8 RAM8 can use the remaining bit?
2. I rmb when doing an exercise in project 1/2, when DMux and Mux were used in the same time.  Their address bit in sel cannot be the same. Why is there a difference?
3. From my observation, those bit of address used only for determining specific register, any other usage for the address?
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

WBahn
Administrator
It's hard to follow exactly what you are asking.

If you give me a RAM8, then I need three bits to address one of the registers in that block.

If you give me eight RAM8 blocks and I feed the same three address bits to each of them, then all eight are accessing one of their registers and I have eight input lines, eight output lines, and eight load signals.

I can tie all of the inputs together so that a single input goes to all eight.

But I can't tie all of the outputs together, I need a way of using a DIFFERENT set of three address bits to choose one of the eight possibilities. How can that be done?

Similarly, I can't tie all of the load signals together because I want to route the load signal to just one of them. How can that be done?

Does that make sense?
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

ajksdf
Thank you for the inspirations ! ! Now, I understand a little more.

The usage of the address bit is used to determine the specific registers. This matches with my observation. However the thing that still confused me most is DMux and Mux need to use same bits of address. Can you explain a little bit more? Thank you
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

WBahn
Administrator
This post was updated on .
Let's see if I can come up with an analogy.

Imagine that I am a planner for a community that is going to house around sixty-five thousand people and I want to be really systematic about how to be able to contact any one of them. So I organize my community into a set of identical neighborhoods and in each neighborhood I build a set of identical apartment buildings, each having a fixed number of floors and with each floor having a fixed number of apartments and which apartment having a fixed number of rooms. Perhaps the following:

Each apartment has 4 rooms (need 2 bits).
Each floor has 8 apartments (need 3 bits).
Each building has 16 floors (need 4 bits).
Each neighborhood as 32 buildings (need 5 bits).
The community has 4 neighborhoods (need 2 bits).

So I can identify a given person's room uniquely in the following way:

[neighborhood][apartment][building][floor][apartment][room]

This can be represented as a 16-bit number with the first two bits being the neighborhood ID and so on.

Now imagine that each room has a light in it and I want to be able to turn on exactly one of those lights by setting a sequence of sixteen switches on a board in a central control room. How might I do that?

When I build an apartment, I bring in three lines. Two of them are the address bits for the four rooms and the third tells that apartment whether to pay attention to what is on the room bits (it tells that apartment if it is the one being selected). This additional bit is analogous to the "Load" signal. So now I can run the same two room selection bits to every apartment in the entire community as long as I only turn on exactly one of the apartment select signals. The wiring in the apartment will use those three pieces of information to decide which, if any, of the four rooms to turn the light on in.

So how do I select an apartment?

I do that at the floor level. In addition to the two room-select bits (which it simply routes directly to each apartment), each floor receives the 3-bit apartment ID as well as a floor-select signal. If uses those four bits of information to decide which, if any, of the apartment select lines on it's floor to assert.

Now we keep walking up. All buildings get the same floor, apartment, and room IDs plus an additional signal that indicates if that building is selected. If it is, then it uses the floor ID to assert the appropriate floor-select line.

At the top level, I route the lower 14 bits to all four communities and I use the top 2-bits to decide which of the four neighborhood select lines to assert.

I hope that helps.
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

ajksdf
Wow. This is quite a good example. I have read it and I think I need to re-read and get a deeper understanding. Thank you for your time. So great to see there are people willing to help other people.
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

ajksdf
In reply to this post by WBahn
Just wanna ask if I pass different addresses bit to Dmux and RAM8. Did those address bits pass to the related place in sequence or they have just been passed down asynchronously? Thank you.
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

WBahn
Administrator
Need more information about what you are thinking in order to make a good answer. There are a few ways to implement these parts. Draw a sketch or post the HDL you are thinking of and that will help us make sure we are on the same page.
Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

ajksdf
In the diagram I draw, for the demultiplexer and the multiplexer. The same bits of address need to be passed in. However, the remaining bits of address need to be be passed to EACH RAM8 as well.

What I would like to ask is that are those address bits are being passed to the suitable place at the same time?

Reply | Threaded
Open this post in threaded view
|

Re: RAM64 address allocation problem within DMux and Mux

WBahn
Administrator
I'm pretty sure I know what you mean, but you need to work on making your diagrams so that they convey the information you want. I don't know what any of these signals are because none of them are labeled. What if I assume that you are using the load line in one place but instead you happen to be using the data lines? All kinds of opportunities for miscommunication.

As for timing, the only parts that have clock signals are individual DFF parts. Unless you are registering some of these signals, they all resolve themselves in the same clock cycle. But that's what we want because when I apply the address, data, and a load signal to a memory block, that is the data that I want written to that address on the next rising edge of the clock. Similarly, if I apply an address line to get data from the chip, that is the address whose data I want to be on the memory block's output on the next rising clock edge.