Ram8

[dmoeller]

So i dont see a fault in my logic but there must be somewhere. I get a comparison error at 4+ when i try to test Ram8. Here is what I have.

IN in[16], load, address[3];
OUT out[16];

Register(in=in, load=load, out=W1);
.
.
.
Register(in=in, load=load, out=W8);
Mux8Way16 (a=W1, ... h=W8, sel=address, out=out);

[ybakos]

When RAM8's load is on, which one of the Registers will store the data? Two of them? Three of them? All of them?

There's something missing.

[dmoeller]

OK I see what you mean. Here is my revised part.

        Mux8Way16 (a=W1, b=W2, c=W3, d=W4, e=W5, f=W6, g=W7, h=W8, sel=address, out=ReadOut);
        Mux8Way16 (a=W1, b=W2, c=W3, d=W4, e=W5, f=W6, g=W7, h=W8, sel=address, out=WriteOut);
        Mux16 (a=WriteOut, b=ReadOut, sel=load, out=out);

I still get comparison error at 4+ though.

[cadet1620]

The tests are much more than just pass/fail. You need to look at the compare and output files. They tell you what is happening.

At time 4+ you will see that the expected output when reading address 0 is 0, but your RAM8 is outputting 11111.

Look back in the compare file and see that at time 1+ the value 0 was written to address 0, and at time 2+ address 0 was read and the value was 0.  The write to address 0 worked.

At time 3+ the value 11111 was written to address 1.  Why did this write to address 1 change the value for address 0?

Something must be wrong with the logic that controls which Register gets loaded for a particular address. (Hint: it's missing.)

--Mark

[dmoeller]

AHA!, i got it. I need a DMux to choose which register gets the load. Got it. Thanks!