Registerbank chip - related to project 5

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Registerbank chip - related to project 5

jojo
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Re: Registerbank chip - related to project 5

jojo
I have set a Dmux4way 3 Dregister and 2 Mux4way16 in parts
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Re: Registerbank chip - related to project 5

cadet1620
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In reply to this post by jojo
jojo wrote
The CPU of the hack machine has only 2 data registers:  A, D. However, most RISC machines have a register bank, usually 32 registers, so that most temporal variables are stored in them instead of using a memory location, which slows down the execution cycle.
Great idea!

There is another bottleneck with the A register because it is used for pointer into memory and jump address and arithmetic constants.

Think about how you might make a loop like this possible using registers only.
// Add RAM[100..109] store sum in RAM[110]
D0 = 0
A1 = 100    (A0 is set by @ commands) 
D1 = 10
while (D1 > 0) {
    D0 = D0 + RAM[A1]
    A1 = A1 + 1
    D1 = D1 - 1
    }
RAM[A1] = D0
This loop requires two A registers. Many loops will want more pointers, for instance to copy data from source array to destination array, so more than two A registers would be a good idea.

One idea would be to replace the current A register with another RegisterBank, but that will add 6 more register select bits.

It might be better to change the RegisterBank to 8 registers, which only adds 3 select bits, and make the registers general purpose. Something like this might work:
  @ instructions always set R7
  Jumps set PC to R7
  addressM is D_b

Have you thought about instruction encoding for your new CPU?

--Mark