Show I worry about this chip?

[GustavoB]

I've just implemented my Not16, I did the following:

CHIP Not16 {
    IN in[16];
    OUT out[16];

    PARTS:
Not(in=in[0],out=x0);
Not(in=in[1],out=x1);
Not(in=in[2],out=x2);
Not(in=in[3],out=x3);
Not(in=in[4],out=x4);
Not(in=in[5],out=x5);
Not(in=in[6],out=x6);
Not(in=in[7],out=x7);
Not(in=in[8],out=x8);
Not(in=in[9],out=x9);
Not(in=in[10],out=x10);
Not(in=in[11],out=x11);
Not(in=in[12],out=x12);
Not(in=in[13],out=x13);
Not(in=in[14],out=x14);
Not(in=in[15],out=x15);
And(a=x0, b=x0, out=out[0]);
And(a=x1, b=x1, out=out[1]);
And(a=x2, b=x2, out=out[2]);
And(a=x3, b=x3, out=out[3]);
And(a=x4, b=x4, out=out[4]);
And(a=x5, b=x5, out=out[5]);
And(a=x6, b=x6, out=out[6]);
And(a=x7, b=x7, out=out[7]);
And(a=x8, b=x8, out=out[8]);
And(a=x9, b=x9, out=out[9]);
And(a=x10, b=x10, out=out[10]);
And(a=x11, b=x11, out=out[11]);
And(a=x12, b=x12, out=out[12]);
And(a=x13, b=x13, out=out[13]);
And(a=x14, b=x14, out=out[14]);
And(a=x15, b=x15, out=out[15]);
}

But I've seen on Cadet's answer here that it should be something like:

Or16(a[0]=x0, a[1]=x1, a[2]=x2,...

Is it problematic to use the implementation I made? I don't know how things are going to end up, perhaps using more components make is less efficient.

[cadet1620]

GustavoB wrote

I've just implemented my Not16, I did the following:

CHIP Not16 {
    IN in[16];
    OUT out[16];

    PARTS:
Not(in=in[0],out=x0);
...
And(a=x0, b=x0, out=out[0]);
...
}

But I've seen on Cadet's answer here that it should be something like:

Or16(a[0]=x0, a[1]=x1, a[2]=x2,...

Is it problematic to use the implementation I made? I don't know how things are going to end up, perhaps using more components make is less efficient.

The post you reference is about how to deal with the "sub bus of an internal node" limitation in HDL. You don't need to worry about that here.

Since it's legal in the And to write "out=out[0]" it's also legal to write it directly into the Not. All you need in your Not16 is 16 Nots.

--Mark

[GustavoB]

Thanks. I was really concerned about efficience issues. Should I erase the code in my last post?

[cadet1620]

GustavoB wrote

Thanks. I was really concerned about efficience issues.

For Nand2Tetris the goal is to learn how to use abstraction to design more complicated parts from simpler parts. For example, it is much easier to understand an And16 built from 16 Ands rather than one built out of 48 Nands. This is even more true for the parts you will build in the chapters leading up to your Computer.

There are multiple, conflicting, optimization goals when designing real hardware. Things like maximizing operating speed, minimizing power usage, minimizing physical size, etc. It's also not too relevant to worry about what may be more efficient for the simulator to run, since we know nothing about how the simulator is implemented.

For Nand2Tetris it helps to keep thinking about how you can use the parts you have recently built in the part you are currently designing.

--Mark