In Section 1.1.4 (of the 1st Ed), the example of building an Xor gate is presented.
For many people, this example causes problems because they don't realize that this example can't be implemented (in the 01 project folder) and run in the Hardware Simulator at this point and so they try to do so. The result of trying to do so is usually the following:
Comparison failure at line 3
Before determining what has been done wrong, let's look as exactly what this error means.
When a test script is executed (and if the necessary commands are present), it produces an output file that is compared to a reference file each time that an output command is executed. If the corresponding lines in the two files do not match, an failure message is generated and the test script is aborted.
After running this Xor test script, the contents of the Xor.out file is:
| a | b | out |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
The contents of the reference file, Xor.cmp, is:
| a | b | out |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
As you can see, the first two lines match, but the third line does not and, hence, the comparison failure message. Note that the first line is the line with the column headers -- the comparison tool is a generic tool that is simply comparing the contents of two files.
But why does the Xor.hdl part produce a 0 output when 'a' is a 0 and 'b' is a 1? The logic in the file would certainly indicate that the output should be a 1.
The problem isn't in the Xor.hdl file at all. The problem is that the Xor.hdl file uses several parts, namely the Not, the Or, and the And, that have not yet been implemented. But the skeleton files for them DO exist in the 01 folder, and so the simulator does find implementations for them, but those implementations do not contain any logic.
Ideally, the simulator would produce some kind of error message when a design uses an output from a part that is not defined. Unfortunately, this simulator generally behaves as if that signal has a 0 value.
There are two ways to deal with this. The first is to define the parts that are used and the second is to force the simulator to use its built-in versions of those parts. The first option doesn't apply in this case, since the whole point of the example is to see how the Xor gate can be implemented before starting the Chapter 01 project. To use the second option, we leverage the fact that when the simulator sees a reference to a part, such as the Not gate in the first line of the Xor logic design, it first looks for an HDL file with that name in the same directory. If it finds it, it loads it; but if it fails to find that file, it uses the built-in model for that part instead.
So one way to get our Xor.hdl to work before implementing the other parts is to delete, move, or rename the HDL files for the Not, the And, and the Or gates.
While this will work, the authors have provided a folder named 'demo' that contains all of the files needed to execute the Xor gate using the built-in chips. This folder isn't mentioned in the test because it was added after the book was published in response to this common stumbling block.
Locked
