Trouble with multibit gates

[paintchip]

Hey guys, I am having a lot of trouble implementing the not16 and and16 gates. However, I think my problem is a syntax one. I am trying to implement the gates by using 16, 1 bit, gates with the syntax; And(a=a[0], b=b[0], out=out[0])..... I have tried several different ways and read Appendix A "buses" a few times, but I still can't get it right. The test scripts keep giving me the failed comparison line. I am getting frustrated with my inability to understand this small part of the HDL language. Can somebody please show me how to properly connect 1 bit from a multibit input to a single bit chip and then send the output to a multibit output? If this is even how I'm supposed to do it :D

[cadet1620]

paintchip wrote

Hey guys, I am having a lot of trouble implementing the not16 and and16 gates. However, I think my problem is a syntax one. I am trying to implement the gates by using 16, 1 bit, gates with the syntax; And(a=a[0], b=b[0], out=out[0])..... I have tried several different ways and read Appendix A "buses" a few times, but I still can't get it right. The test scripts keep giving me the failed comparison line. I am getting frustrated with my inability to understand this small part of the HDL language. Can somebody please show me how to properly connect 1 bit from a multibit input to a single bit chip and then send the output to a multibit output? If this is even how I'm supposed to do it :D

You've definitely got the right idea, and your And syntax looks correct.  One thing to try is to move your And16 files into a subdirectory by themselves and test them there.  That way you'll be testing only your And16 (using the built-in And).  If it works in isolation then there must be a problem with your And or Not. (Not likely unless they somehow got changed after they past their tests.)

Look at the output and compare files for the test line that fails and see what bit is failing and take a close look at that bit's And gate.  Note that the bit numbers in [] are numbered from right to left.

If you can't find it, send me your HDL and I'll be happy to take a look at it.  (Use More|Reply to Author)

--Mark

[paintchip]

So it turns out that my implementation was correct, but there was something screwy with the directory I was testing the scripts in. I unpacked the zip file into its own directory and when I move my .hdl files into that directory, or use the shell files from the zip in that directory, I always get 0s for "out" in my output file. When I move the .tst, .hdl, and .cmp files to another directory it works fine. The permissions are the same for both directories, but the unix unzip utility may do something weird to the files. I was pulling my hair out trying to figure out the HDL syntax that I had right all along :D

[cadet1620]

One thing to be aware of is that the Hardware Simulator does not complain if a chip's output is not connected to anything; disconnected outputs default to 0.

One implication of this is that if you have the skeleton files without implementations in your working directory they will supersede the built-in chips but always output 0.  It is therefore necessary to build the chips in the order listed in the book to avoid using chips you have not yet written.

--Mark