Why does the first implementation work but the second one doesnt for 8 way demux?

[nblackburn]

CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;

    PARTS:
    // This works
    // DMux(in=in, sel=sel[2], a=outA, b=outB);
    // DMux4Way(in=outA, sel=sel[0..1], a=a, b=b, c=c, d=d);
    // DMux4Way(in=outB, sel=sel[0..1], a=e, b=f, c=g, d=h);

    // This does not work: "an internal pin may only be fed once by a parts output in"
    DMux(in=in, sel=sel[2], a=outA, b=outB);
    DMux(in=outA, sel=sel[1], a=outA1, b=null);
    DMux(in=outB, sel=sel[1], a=null, b=outB1);
    DMux4Way(in=outA1, sel=sel[0], a=a, b=b, c=c, d=d);
    DMux4Way(in=outB1, sel=sel[0], a=e, b=f, c=g, d=h);
}

I am wondering why the former implementation works but the latter doesnt. I dont really understand how I did the first implementation, I understand what a 8 way demux is meant to do but I am not sure how the way I did it actually works. My first attempt was the latter implementation and I can understand why I was previously getting the error "Sel (1) and sel (2) have different bus widths" since I was using sel[2] once and sel[1] once, when actually sel[2] is double the width of sel[1] but now when I fixed that error, I get the internal pin error. It makes sense to my how this would work, both dmux's with sel[1] would feed the output pin into the 4way demux chips and then the 4way demux chips would output the final outputs and I know what the former implementation is more efficient since it uses less chips but I just dont fully understand how it works. I watched a video on implementing the chips and his way made sense to me. I watched it and waited a day to re-do the gate on my own, and did it from memory but I have this nagging feeling I just dont fully understand how it actually works.

[nblackburn]

I have drawn out the diagram for an 8 way demux and it makes sense to me that way. I have made the HDL code for it but I just dont quite get the error: "sel(2) and sel(1) have different widths". I thought I understood (mentioned in post I am replying to) it but I dont.

If sel = 000, then surely sel at each index is == 0. In which case they all have the same width? Or does it work like sel[2] == 000, sel[1] == 00, sel[0] == 0; but then if that is the case then how does my code for a 4 way mux work:

    Mux16(a=a, b=b, sel=sel[0], out=out1);
    Mux16(a=c, b=d, sel=sel[0], out=out2);
    Mux16(a=out1, b=out2, sel=sel[1], out=out);

sel[0] and sel[1] would be different widths, no?

I have read appendix 2.2 on multi-bit buses but I still just dont understand how it works. I have a decent amount of programing experience and I thought that indexing in a programming language would work the same as indexing here. e.g. the int 8000 when indexed would be int[0] == 8, int[-1] == 0 etc.

I would really appreciate an explanation on this, since it logically makes sense to me but I am just not sure what is causing the error.

[dolomiti7]

I'll try to clarify the syntax:

In the case of the DMux8Way, your input signal "sel" has a width of 3 (think of it as 3 bits or 3 signals), as defined here:
IN in, sel[3];
With the 3 signals, each having one of the 2 states (0 or 1) you can address 2^3=8 of the output lines.

Respectively for the DMux4Way, the width of the input "sel" is 2 (->2^2=4), which you can also see in the provided stub HDL file for DMux4Way.
And finally for DMux the input "sel" is just a single input (->2^1=2), allowing to select one of the two output signals.
When you want to connect the "sel" signals inside the DMux8Way where it has a width of 3 with some other module which expects a different input width you have to define which of the 3 signals to connect.

The logic is as follows: (assuming sel has been defined as IN sel[8] as an example)
1. Single bit:
input[n] = addresses exactly one of the bits of input; n can range from 0 to 7 in this example with a definition of sel[8]; since it represents a single signal, the width in this case is always 1! E.g. you can connect this only to another input of width 1!
Therefore DMux4Way(in=outA1, sel=sel[0], a=a, b=b, c=c, d=d) doesn't work, since sel of DMux4Way is expecting a width of 2, while sel[0] is only 1 bit wide.
2. Range:
input[m..n] = addresses a range of bits of input; the width in this case is n-m+1. Example: input[4..6] has a width of 3 and could be connected to any input that expects a width of 3.

Hope that helps

[nblackburn]

Thank you for the explanation. I understand it now!