Xor gate

[JD Steffen]

Hello, I think I may have found a problem with the hardware simulator. I have the following HDL:

CHIP Xor {



    IN  a, b;

    OUT out;



    PARTS:

    Not(in=a, out=OrBA);
    Not(in=b, out=OrBB);

    Or(a=a, b=b, out=gatea);
    Or(a=OrBA, b=OrBB, out=gateb);

    And(a=gatea, b=gateb, out=out);

}

The problem is that the Or gate connected to the two Not gates will not output a 1 when one of the inputs is high. I have confirmed that this design works in another logic simulator. I am new to digital logic and using gates, so I might be missing something elementary here.

I am using the 2.5 version of the software suite and the other simulator that I used is Logisim 2.6.2.

Thanks for any help you can provide.

[cadet1620]

JD Steffen wrote

The problem is that the Or gate connected to the two Not gates will not output a 1 when one of the inputs is high. I have confirmed that this design works in another logic simulator. I am new to digital logic and using gates, so I might be missing something elementary here.

Your design works for me in v2.5. Try testing it in a directory without any other HDL files in it. This will force the simulator to use the built-in version of the Not, Or and And chips. There may be a subtle problem with one of yours.

You can also change the Xor.tst file to not stop on miscompare and to output your internal signals:

    // compare-to Xor.cmp,
    output-list a%B3.1.3 b%B3.1.3 OrBA%B3.1.3 OrBB%B3.1.3 gatea%B3.1.3 gateb%B3.1.3 out%B3.1.3;

This may give you more clues about what's happening. Here's what my output looks like running your Xor:

    |   a   |   b   | OrBA  | OrBB  | gatea | gateb |  out  |
    |   0   |   0   |   1   |   1   |   0   |   1   |   0   |
    |   0   |   1   |   1   |   0   |   1   |   1   |   1   |
    |   1   |   0   |   0   |   1   |   1   |   1   |   1   |
    |   1   |   1   |   0   |   0   |   1   |   0   |   0   |

--Mark