.hdl file won't load after changes are made

[Bryan M]

Hello,

I have simulator up and running.  I'm able to put the hdl and txt files in the simulator and play around with them.  I am able to open a hdl file into a text editor (I've used notepad and notepad++).

Then we get to the problem.  After I make the changes in the hdl file and save these changes.  Then I am not able to open the hdl file into the simulator.

Any advice?  I need to get this working as soon as possible.

[WBahn]

When you say that you can't open the hdl file into the simulator, what exactly does that mean? What is the indication that you are seeing that it didn't load? What is the message at the bottom of the simulator window (you may need to maximize the window to see it)?

[Bryan M]

I've added a screen shot of what I'm talking about.

[WBahn]

Your And.hdl file has no code. The simulator can't load code that doesn't exist.

[Bryan M]

Thanks.  I was able to figure it out.

Can I get some help with just how to write the hdl?  I figured out the Not and the And, but I can't wrap my head around Or and if I'm being honest, I'm not 100% sure how I got Not and And.  I've watched all the videos multiple times, I've read over the books, and looked over the forum.  I know we don't want the code posted here, but I'm a visual learner and I just need to see how it is done.

[WBahn]

One way is to put the truth table for the Nand gate in one column and the truth table for the gate you want in another column. In the case of the Not, you only have one input, so let's use 'a' as our 'in'.

a  b  Nand  Not
0  0     1      1
0  1     1      1
1  0     1      0
1  1     0      0

Notice that if we force 'b' to 'false' that this reduces to

a  b  Nand  Not
0  0     1      1
1  0     1      0

While if we force 'b' to 'true it reduces to

a  b  Nand  Not
0  1     1      1
1  1     0      0

Another option is to force 'b' to be whatever 'a' is

a  b  Nand  Not
0  0     1      1
1  1     0      0

Do any of these result in the output of the Nand being what you want the output of a Not to be?

If so, then all you have to do is wire up the part so as to impose the appropriate constraint.

Once this is done, you now have two parts in your tool box that you can use, Nand and Not.

For the And, think about the "double negative" that we are always getting chastised about in English.

Nand is short for "Not And", so what would "Not Not And" be equivalent to?

For Or, remember that you can use a Not gate to invert either or both input signals before it gets to the Nand and only to invert the signal after it comes out. So that's three places you can optionally either use or not use a Not gate, yielding eight possibilities. Try all eight and see which, if any, of them yield the same output as an Or gate.
 

[Bryan M]

Can you show me how that would be written for the hdl code?  

[WBahn]

Bryan M wrote

Can you show me how that would be written for the hdl code?

How what would be written?

You do not write truth tables in HDL, you wire together parts that implement a truth table.

Start by indicating which of the truth tables I've presented you want to implement.

[WBahn]

You said that you got the Not and And to work. How? Did you just find some code on some github site or similar? Or did you just make random changed hoping that, at some point, something good would just happen?

Whatever it may be, you have a working design for those two parts. So start with walking through those designs, signal by signal, from input(s) to output and figure out how they work.