help with demux4way

[phoenix]

I try to bulid demux4way using and and not gate
    Not(in=sel[0], out=notsel0);
    Not(in=sel[1], out=notsel1);
    And(a=notsel0, b=notsel1, c=in, out=a);
    And(a=sel[0], b=notsel1, c=in, out=b);
    And(a=notsel0, b=sel[1], c=in, out=c);
    And(a=sel[1], b=sel[0], c=in, out=d);
 
i found internal pins notsel1 and notsel0 are always 0

why ?

 thank you in advance

[WBahn]

What is this 'c' input on your And gate?

Just to be sure that nothing simple has been missed...

Are you sure your Not gate is working properly?

Are you sure that your sel[0] and sel[1] signals are taking on various values (i.e., that they aren't stuck at 1 all the time)?

Try stepping back and make your part just output the inverted sel signals to two of the output pins. Get rid of the And gates altogether. You might add two more Not gates and invert the inverted sel signals and output those to the other two outputs.

See if that works correctly.

[WBahn]

Your logic is on the right track, you just need to be sure to conform to the constraints of the parts you have available.

Your logic implies that your And gates need to be 3-input And gates. But the And gate specification is for a 2-input And gate. If you want to make a 3-input And gate (perhaps call it And3), then you can certainly make that part and use it in your design. That's perfectly legitimate and allowed. You don't NEED to do that, however -- the authors were very careful to give you the specs on a set of gates that are sufficient to complete the projects. But if your thinking leads you to do it a different way, that's fine.

Let's focus on just one condition -- your Demux has several output channels (four of them). Let's think of one of the channels (let's pick channel 2, which is when sel[1]=1 and sel[0]=0) and forget about the rest. When THAT channel is selected, you want to echo the input to that channel's output, otherwise you want that output to be zero. Let's assume that we have a signal called sel2 which is a 1 when channel 2 is selected and 0 otherwise. What is the logic to combine the sel2 signal with the input signal to get the channel 2 output signal? What is the logic to combine sel[1] and sel[0] to get the sel2 signal?