Re: Trobles implementing some of the chips in HDL

Posted by culchie on Jan 27, 2010; 10:20am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Trobles-implementing-some-of-the-chips-in-HDL-tp138687p140475.html

If you have 4 inputs (a, b, c, d) their addresses will be represented in binary by 00, 01, 10, 11.
In your sel array the sel[0] corresponds to the lsb bit.
Therefore you can use a mux with sel[0] as the sel bit to decide between a and b and another mux with
sel[0] also as the sel bit to decide between c and d.
Call the outputs of these 2 muxs e and f.
The address for e will be either 00 or 01 while the address for f will be either 10 or 11
Now to get the final output you have to pick one of e or f

If people feel this is inappropriate I'll edit it. I figured since there's no hdl it's allowed

EDIT looking at what i wrote above, I don't know if I should have used the word 'address'. The point I was trying to make was that if you think of the Mux as having 4 input slots these from the MUX's point of view
would be be 00, 01, 10 11