Re: Not test failing

Posted by cadet1620 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Not-test-failing-tp2536858p2537284.html

This is a bit of a trap in the HDL language.  The output of the Nand gate is connected to internal wire "c" which goes nowhere.  You have not connected anything to the "out" output of the Not chip.  There are no error messages or warnings associated with this type of problem.

--Mark