Re: De-bus pins?

Posted by cadet1620 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/De-bus-pins-tp2802816p2803599.html

mmiller7 wrote

I'm working on the CPU and I wonder if there's any easy way to reference a sub-bus without using lots of extra gates?

I don't think that there is a way to alias I/O wire names in HDL.  You can alias internal wire names by having multiple 'out=' in a part statement.

FWIW, I have this layer of ANDs in my CPU, but they AND with instruction[15].  Although not necessary for the Hack CPU, experience makes me qualify all the C-instruction control signals so that they are in a defined state during A-instructions.

A few extra AND gates in the CPU are trivial -- The RAM16K contains > 13 million NAND gates!

--Mark