Re: De-bus pins?

Posted by cadet1620 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/De-bus-pins-tp2802816p2805003.html

mmiller7 wrote

Ah, ok.  That does make sense...when you're talking about millions of gates a dozen really is trivial.

Designing real-world hardware I think I can understand why it might be desirable to specify what happens to sub-componants when they are "inactive" but I felt like for the purpose fo the HACK computer it shouldn't really matter.  During an A-instruction I wrote it so the output of my ALU goes nowhere so I felt like it would be redundant to try and specify what it's doing.  I suppose it all depends how the data is going to be used as to what the state should be.

Quite right.  In the Hack CPU it doesn't matter if random things are happening in the ALU during A-instructions.  In my design, even though all the control signals are gated by C-instruction, random data still appears on the outM bus during A-instructions since the ALU's computing A&D, but that doesn't matter since writeM is not set during A-instructions.

Being systematic about things like this can help if a project is passed from one engineer to another, or if you have to revise your own work a year or two later when you no longer remember all the little details.  It can also help in debugging; signals on logic analyzer or oscilloscope are easier to understand if they aren't doing random things half the time.

--Mark