Re: Building chips problem.

Posted by GustavoB on Oct 31, 2011; 9:16pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Building-chips-problem-tp3468285p3469076.html

I understand. I've been researching about HDL, the most used languanges are the Verilog and VHDL, acording to wikipedia. I just don't know if the logical functions on Verilog or VHDL will work on the hardware simulator, but i'm going to try that now. I still don't know if the languange is a standard on both the TECS software, verilog and VHDL. I'm starting to think that it is but what motivated me to think they're different is that HDL could be a end, and VHDL/Verilog/Tecs software could be different means to this end.