Re: confused on Figure 1.6 implementation of Xor gate

Posted by cadet1620 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/confused-on-Figure-1-6-implementation-of-Xor-gate-tp3706181p3706370.html

The schematic drawing at the top of Figure 1.6 is the canonical representation of Xor.

HDL is a description of this schematic. Each logical function in the schematic gets a line in the PARTS: section of the HDL, describing how wires are connected to it.

Make sure that you have downloaded the HDL stub files and test scripts. All you need to add to the Xor.hdl stub file are the Nots, Ands and Or.

WARNING, If you have not implemented Not.hdl, And.hdl and Or.hdl this chip will not work because those stub files have empty implementations. Make a subdirectory and move the Xor.* files into it if you want to work with Xor before you make the chips it uses.

--Mark