Re: confused on Figure 1.6 implementation of Xor gate

Posted by ybakos on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/confused-on-Figure-1-6-implementation-of-Xor-gate-tp3706181p3706870.html

Hey Erik,
Did you implement Not, Or and And? As Mark states, you should implement the chips in the project according to the order they are listed in the project page.

The w1 and w2 you see in figure 1.6 are user-defined pins. The names are arbitrary. For example:

MyChip(in=x, out=mySpecialPin);
MyOtherChip(in=mySpecialPin, out=out);

You need to imagine that "wire x" is connected to the input of MyChip, and the output of MyChip is connected to a wire called mySpecialPin. Next, the wire mySpecialPin is connected to the input of MyOtherChip.

Now, in regards to your Xor problem -- take a look at the diagrams. The implementation is right there.

Keep working at this -- once you get used to the HDL things will come together.