Re: confused on Figure 1.6 implementation of Xor gate

Posted by ybakos on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/confused-on-Figure-1-6-implementation-of-Xor-gate-tp3706181p3707822.html

It's just the name of the wire. Look at Mark's diagram. What is the input to the lower AND gate? It is a wire called "NotA." Where did that wire come from? It is the output of the Not gate.

That wire could be called "elephants," "chicken" or "pumpkin."

Given the syntax of the Hack HDL, how else would you be able to specify that "the wire coming out of the not gate is an input to an and gate" ?