Re: Condition to logic

Posted by ivant on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Condition-to-logic-tp4034355p4034367.html

Yes, exactly!

Now you have two gates; exposes its in input when sel == 1 and the other one exposes its in when sel == 0. You need to somehow combine them to produce the specification of mux.