Re: Chapter 1 efficiency considerations

Posted by WBahn on Jul 11, 2020; 1:17pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Chapter-1-efficiency-considerations-tp4034841p4034842.html

The goal is to achieve a correctly functioning implementation.

There is no consideration for "efficiency", which is an ambiguous concept anyway unless the metric for it is clearly defined -- fewest transistors, fastest speed, etc.

Consider the Not gate. Yes, that can be implemented with a single Nand gate, but a Nand gate (in standard CMOS) requires four transistors, but a Not gate can be directly implemented using just two transistors and be slightly faster.

Even more to the point, how would you implement a 2-input Nor gate? In standard CMOS, it is a done with four transistors and is essentially the same speed as a 2-input Nand gate. But if you have to build it out of Nand gates, you are looking at needing four Nand gates for a total of sixteen transistors and it will be only a third the speed.

So the very notion of constructing a computer with nothing but Nand (and DFF) chips means that the focus is on a seeing a clear structural hierarchy at the expense of anything related to performance. No one in their right might would ever build a real computer this way, but understanding exactly how it could be done has tremendous educational value.

Having said all of that, while there is no need to try to come up with elegant implementations for any of the parts, there is no harm in doing so, either, and the practice in manipulating logic circuits has value.