Comparison Failure for And or Or gates

Posted by Idrisadeniyi on Jan 28, 2021; 1:11pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Comparison-Failure-for-And-or-Or-gates-tp4035543.html

Good Day;

For a while now, I have been stuck on this And and Or chips in hdl. I have written the truth tables and have also drawn the gates; and I was able to figure out the combination of gates I need to use to implement each of them.

However, for hours now, I have been stuck. The simulator keeps outputting a 'comparison failure error' message. I know for definite that something is inherently wrong with my hdls, but I could not identify the glitch.

The following is my hdl codes for both And and Or gates.

Please assist!
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/And.hdl

/**
 * And gate:
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    // Put your code here:
        Not (in=a, out=nota);
        Not (in=b, out=notb);
        Nand (a=a, b=nota, out=x);
        Nand (a=notb, b=x, out=out);
       
}


// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Or.hdl

 /**
 * Or gate:
 * out = 1 if (a == 1 or b == 1)
 *       0 otherwise
 */

CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    // Put your code here:
        Not (in=a, out=nota);
        Not (in=b, out=notb);
        And (a=a, b=notb, out=x);
        And (a=nota, b=b, out=y);
        And (a=x, b=y, out=out);
       
}