Posted by
WBahn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Mux4way16-problem-tp4035690p4035713.html
Idrisadeniyi wrote
Ok. So am I suppose to have something like sel[00] [01]...[11]?
If so, anytime I have the left bit higher than the right, I get an error message: "The specified sub bus is not in the bus range" like this: sel[10] and [11].
That's because you sel bus doesn't have a wire #10 or a wire #11.
It seems like you are confusing the values of the data on a signal and the wires that make up that signal.
Remember, the HDL code merely describes how wires are connected. Nothing more. NOTHING more.
Buses are nothing more than a collection of wires, number 0 through one less than the number of wires in the bus.
Let's make up a simple logic function and see how we would implement it.
CHIP MyChip
{
IN fred[16], sue[16];
OUT y[2];
PARTS:
Or16(a[0..7]=fred[4..11], a[8..15]=sue[1..8], b=fred, out[4]=y[0], out[13]=y[1]);
}
The Or16 gate has two 16-bit inputs and a 16-bit output.
The notation signal[number] means "Wire #<number> in the bus named <signal>".
So we have the following:
a[0] of the Or16 gate input is connected to fred[4] of the chip's input.
a[1] of the Or16 gate input is connected to fred[5] of the chip's input.
a[2] of the Or16 gate input is connected to fred[6] of the chip's input.
...
a[7] of the Or16 gate input is connected to fred[11] of the chip's input.
a[8] of the Or16 gate input is connected to sue[1] of the chip's input.
a[9] of the Or16 gate input is connected to sue[2] of the chip's input.
...
a[15] of the Or16 gate input is connected to sue[8] of the chip's input.
Since the 'b' input of the Or16 gate and 'Fred' are of the same width, they can be connected directly with the understanding that:
b[0] of the Or16 gate input is connected to fred[0].
b[1] of the Or16 gate input is connected to fred[1].
...
b[15] of the Or16 gate input is connected to fred[15].
There are several input wires, namely sue[0] and sue[9..15] that are not connected. That's fine.
The output consists of two wires and we need to connect them both. We are connecting one of them to one of the Or16 gate outputs and the other to a different one. We have fourteen other outputs from the Or16 that are not being used, which is fine.
out[4] of the Or16 gate output is connected to y[0] of the chip's output.
out[13] of the Or16 gate output is connected to y[1] of the chip's output.