Re: multiplexor / demultiplexor and communications networks (general question)

Posted by WBahn on Apr 21, 2023; 1:56pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/multiplexor-demultiplexor-and-communications-networks-general-question-tp4037109p4037124.html

Whatever is looking at the outputs of the dmux knows when its data is present and when it is not.

This is often done using a DFF (which you will get to in the Chapter 3).

So let's say that you have two data lines coming in with data changing every two seconds.

Your select line changes state every second, so that data on the transmission link on even-numbered seconds is data from the first line while odd-numbered seconds it is from the second line.

At the output of the dmux, the data on the first output is valid data from the first line during even-numbered seconds but it is garbage during odd-numbered seconds. The situation is flipped for the second output.

Following the dmux, you have a register that looks at the data during each even-numbered second and loads that value into the register and holds it for two seconds so that it remains stable and ignored the garbage during the odd-numbered seconds. The other line has a similar set-up.