Re: Why does the first implementation work but the second one doesnt for 8 way demux?

Posted by nblackburn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Why-does-the-first-implementation-work-but-the-second-one-doesnt-for-8-way-demux-tp4037705p4037706.html

I have drawn out the diagram for an 8 way demux and it makes sense to me that way. I have made the HDL code for it but I just dont quite get the error: "sel(2) and sel(1) have different widths". I thought I understood (mentioned in post I am replying to) it but I dont.

If sel = 000, then surely sel at each index is == 0. In which case they all have the same width? Or does it work like sel[2] == 000, sel[1] == 00, sel[0] == 0; but then if that is the case then how does my code for a 4 way mux work:

    Mux16(a=a, b=b, sel=sel[0], out=out1);
    Mux16(a=c, b=d, sel=sel[0], out=out2);
    Mux16(a=out1, b=out2, sel=sel[1], out=out);

sel[0] and sel[1] would be different widths, no?

I have read appendix 2.2 on multi-bit buses but I still just dont understand how it works. I have a decent amount of programing experience and I thought that indexing in a programming language would work the same as indexing here. e.g. the int 8000 when indexed would be int[0] == 8, int[-1] == 0 etc.

I would really appreciate an explanation on this, since it logically makes sense to me but I am just not sure what is causing the error.