Re: Why does the first implementation work but the second one doesnt for 8 way demux?

Posted by dolomiti7 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Why-does-the-first-implementation-work-but-the-second-one-doesnt-for-8-way-demux-tp4037705p4037707.html

I'll try to clarify the syntax:

In the case of the DMux8Way, your input signal "sel" has a width of 3 (think of it as 3 bits or 3 signals), as defined here:
IN in, sel[3];
With the 3 signals, each having one of the 2 states (0 or 1) you can address 2^3=8 of the output lines.

Respectively for the DMux4Way, the width of the input "sel" is 2 (->2^2=4), which you can also see in the provided stub HDL file for DMux4Way.
And finally for DMux the input "sel" is just a single input (->2^1=2), allowing to select one of the two output signals.
When you want to connect the "sel" signals inside the DMux8Way where it has a width of 3 with some other module which expects a different input width you have to define which of the 3 signals to connect.

The logic is as follows: (assuming sel has been defined as IN sel[8] as an example)
1. Single bit:
input[n] = addresses exactly one of the bits of input; n can range from 0 to 7 in this example with a definition of sel[8]; since it represents a single signal, the width in this case is always 1! E.g. you can connect this only to another input of width 1!
Therefore DMux4Way(in=outA1, sel=sel[0], a=a, b=b, c=c, d=d) doesn't work, since sel of DMux4Way is expecting a width of 2, while sel[0] is only 1 bit wide.
2. Range:
input[m..n] = addresses a range of bits of input; the width in this case is n-m+1. Example: input[4..6] has a width of 3 and could be connected to any input that expects a width of 3.

Hope that helps