16-bit Questions

[Technik]

Hey,

I've managed to successfully implement NOT16, but I'm concerned about the redundancy of lines when using my previously built chips in HDL. I don't want to give away a possible implementation, so hopefully what I'm saying makes sense.

Anyway, when I try to subscript it to remove the redundancy, I get the error "Line 15, in(1) and in(16) have different bus widths."

I'm using the notation found in A.5.3.

Any ideas?

[ybakos]

Remember, HDL is not describing software, it is describing hardware. How would you build a Not16 with 1-bit Not gates in the real world? You'd wire each of them up.

In other words, the repetition is ok.

[Technik]

Aha! Thanks

Back to the simulator!

[cadet1620]

The error is telling you that in for your Not chip is a single wire and that in for your Not16 chip is a 16-wire bus. Since you need to connect each of the 16 wires in the bus to an individual Not chip, you will need 16 Not chips in your Not16. A.5.3 shows how to select individual wires or groups of wires from a bus. There is no looping construct in HDL.

--Mark

[adijo]

Because there is no looping construct in HDL, we could use a higher level language like Python to do the repetitive work for us. I did the following for And16 for example:

def producer(x):
        print "Nand(a=a[%d],b=b[%d],out=w%d);" % (x,x,x)
        print "Nand(a=w%d,b=w%d,out=out[%d]);" % (x,x,x)
        print "\n"

for x in range(16): producer(x)