A little bit of amusement with Mux4Way

[IronP]

So comrades, I've used a little bit of time developing a 4 way multiplexor with nands, but for some motive it is not giving me the expected output.
It was my first try, and it occupies 28 nand gates when it could occupy only 21, but for now it's just a case study.
I've analised it some times, and can't find where the error is. I've developed a .tst and an .cmp to it, but when the output of A, B, C, D, S[0], S[1](0, 0, 0, 0, 0, 0) is being 1.
Doing the same test manually the output is 0 (maybe I'm failing in realising something, but if so, I've failed some times).
Well, here is the code:

CHIP Mux4Way {
    IN a, b, c, d, sel[2];
    OUT out;

    PARTS:
    Not(in=a, out=an);                             //Beginning the Not definitions
    Not(in=b, out=bn);
    Not(in=sel[0], out=s0n);
    Not(in=sel[1], out=s1n);
    Not(in=c, out=cn);
    Not(in=d, out=dn);                              //End
    Nand(a=an, b=s0n, out=out00);            //First step of selection
    Nand(a=sel[0], b=bn, out=out01);
    Nand(a=out00, b=out01, out=out10);     //End (out10)
    Nand(a=s0n, b=sel[1], out=outs00);       //Defining if Sel[0]=0 then true
    Nand(a=s0n, b=s1n, out=outs01);
    Nand(a=outs00, b=outs01, out=outs1);   //End (outs1)
    Not(in=outs1, out=outs1n);                   //Defining Not outs1
    Nand(a=cn, b=outs1, out=out02);          //Second step of selection
    Nand(a=outs1n, b=dn, out=out03);
    Nand(a=out02, b=out03, out=out11);      //End (out11)
    Nand(a=s0n, b=sel[1], out=outs10);        //Defining if Sel[1]=1 then true
    Nand(a=sel[0], b=sel[1], out=outs11);
    Nand(a=outs10, b=outs11, out=outs0);    //End (outs0)
    Not(in=out10, out=out10n);              //Defining Not first selection
    Not(in=outs0, out=outs0n);              //Not (if Sel[1]=1 then true)
    Not(in=out11, out=out11n);              //Not second selection
    Nand(a=out10n, b=outs0n, out=out1);     //Third step of selection
    Nand(a=outs0, b=out11n, out=out2);
    Nand(a=out1, a=out2, out=out);          //End
}

So, what's happening?

Cheers!

[ybakos]

Have fun experimenting! Be careful that your .tst and .cmp are accurate and don't mislead you.

I'm curious, why are you only using Nand and Not chips? Is that part of your experiment? (If you built one Mux, building a Mux4Way should be pretty straightforward...)

[IronP]

I'm having a lot of fun (thanks!) and took the nand and not construction thing as a challenge. I didn't realize before "finishing" this design how I would use the Muxes conjointed, but when I did I had a good laugh.

But about the tests, I have this list of internal pins provided by the simulator that indicates all the pins correctly as expected. It seem that only the output is being troublesome. I'll only paste here the first part of the .tst:

"load Mux4Way.hdl,
output-file Mux4Way.out,
compare-to Mux4Way.cmp,
output-list a%B3.1.3 b%B3.1.3 c%B3.1.3 d%B3.1.3 sel%B3.2.3 out%B3.1.3;

set a 0,
set b 0,
set c 0,
set d 0,
set sel %B00, //edit: added "%B"
eval,
output;"

And the expected output:

"
|   a   |   b   |   c   |   d   |  sel   |  out  |
|   0   |   0   |   0   |   0   |   00   |   0   |"


Also, here is the whole list of pin configuration of this test:

"
an     1
bn     1
s0n     1
s1n     1
cn     1
dn     1
out00     0
out01     1
out10     1
outs00     1
outs01     0
outs1     1
outs1n     0
out02     0
out03     1
out11     1
outs10     1
outs11     1
outs0     0
out10n     0
outs0n     1
out11n     0
out1     1
out2     1"

Except for the final output, that's returning 1.

Edit:
Found it! I have two "a" inputs in the final nand gate.
Thanks for your attention. I'll probably need some more sometime haha.
Cheers!

[cadet1620]

You can do Mux4Way with a lot fewer Nand gates.

First make a Mux with Nand gates. (Not can be considered a "one input" Nand gate.)
Use 3 of these Nand Muxes to make a Mux4Way in the same way you can make Mux4Way16 from 3 Mux16s.

--Mark