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On the first chapter, they say that youre encouraged to build your own chips to use them on further projects. I could build the NAND chip using the examples from pages 16 and 282. I've noticed this:
-Appendix A comes with no description on logical functions. Isn't that needed for building the chips?
-I've built my NAND chip this way:
/* Nand gate */
CHIP Nand {
IN a, b;
OUT out;
PARTS:
And(a=a, b=b, out=c);
Not(in=c, out=out);
}If the HDL recognize functions like and, not and xor, why build this chips?
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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GustavoB wrote
On the first chapter, they say that youre encouraged to build your own chips to use them on further projects. I could build the NAND chip using the examples from pages 16 and 282. I've noticed this:
-Appendix A comes with no description on logical functions. Isn't that needed for building the chips?
-I've built my NAND chip this way:
/* Nand gate */
CHIP Nand {
IN a, b;
OUT out;
PARTS:
And(a=a, b=b, out=c);
Not(in=c, out=out);
}
If the HDL recognize functions like and, not and xor, why build this chips?
Do not build the Nand chip. It is the fundamental built-in chip that all other chips are derived from.
The description of the chips that you need to build are in Chapter 1. You will build the And and Not chips. If you write a Nand.hdl file you will end up with recursive definitions: Nand needs Not needs Nand needs ....
The reason to build all the other gates is to learn how to do it. The skills you learn will help you with more complicated designs like your CPU. (And to get a passing grade if you're taking TECS as a proctored course. 8^)
--Mark
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cadet1620 wrote
The reason to build all the other gates is to learn how to do it. The skills you learn will help you with more complicated designs like your CPU. (And to get a passing grade if you're taking TECS as a proctored course. 8^)
I know, but shouldn't the book bring info on the implementation of logical functions in HDL?
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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The authors' beliefs, and my experience as a math instructor, is that students learn and retain information much better if they need to research and experiment a bit to get to solutions.
As you saw, the example in Appendix A and the Xor example gave you the information you needed to write syntactically correct HDL, and the Xor example teaches how to realize an HDL file from a circuit design.
One thing to watch out for is that the stub files provided do not contain implementations so it is important to implement the chips in the order in section 1.3. If you implement Xor as in Figure 1.6 before implementing And, Or and Not, it will not work correctly.
Also, read Hardware Construction Survival Kit for more useful hints.
--Mark
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I understand. I've been researching about HDL, the most used languanges are the Verilog and VHDL, acording to wikipedia. I just don't know if the logical functions on Verilog or VHDL will work on the hardware simulator, but i'm going to try that now. I still don't know if the languange is a standard on both the TECS software, verilog and VHDL. I'm starting to think that it is but what motivated me to think they're different is that HDL could be a end, and VHDL/Verilog/Tecs software could be different means to this end.
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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GustavoB wrote
I understand. I've been researching about HDL, the most used languanges are the Verilog and VHDL, acording to wikipedia. I just don't know if the logical functions on Verilog or VHDL will work on the hardware simulator, but i'm going to try that now.
TECS HDL is a very simple-minded language. Verilog and VHDL constructs will not work. Exactly what's documented in Appendix A, no more, no less.
--Mark
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So it isn't need to implement the AND, OR, XOR and NOT, right?
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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The point of chapters 1, 2, 3 and 5 is for you to implement all the chips yourself except for NAND and DFF (chapter 3) which are fundamental built-in chips. The chapter .zip files contain stub HDL files for the chips you need to build in each chapter. It is important to build the chips in the order specified in the Implementation section of each chapter since later chips depend on prior chips having been implemented.
The built-in versions of the chips from earlier chapters are used by later chapters for simulation efficiency. For instance, trying to simulate a 16K RAM built up from NAND gates and DFFs would run too slow to be useful (and would probably not be able to be loaded in the simulator due to system memory limitations).
--Mark
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I did my NOT chip like this:
/* Not */
CHIP Not {
IN in;
OUT out;
PARTS:;
Not(in=in, out=out);
}
But it does not work, it comes up with the error:
In HDL file Not.hdl, Line 6, A GateClass name is expected.
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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You need to build your Not chip using Nand. Look at the truth table for Nand. What can you do with the a and b inputs to make it function as a Not?
--Mark
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Ahhh, ok.
According to the table, making the a input being always 1 and using the b input as the input for the not, like:
/* Not gate */
CHIP Not {
IN b;
OUT out;
PARTS:
Nand(a=1, b=b, out=out);
}
I just can't test it now, my HardwareSimulator keeps on eternal loading. I gonna reboot and i hope this fixes it.
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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This post was updated on .
Changing the name of inputs and/or outputs in the skeleton HDL files
will be a problem for you but please don't post functional HDL in the
forums. It is better if everyone has the opportunity to discover the
correct implementations for themselves.
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Administrator
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You can't say 'pin=1' in HDL. Read Appendix A.5.2 to learn about constants.
--Mark
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I had an error: Chip Part1 is not found in the working and built in folders.
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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GustavoB wrote
I had an error: Chip Part1 is not found in the working and built in folders.
You need to give us more information so that we can help you effectively.
This error message says that you have a line like
Part1(...)
in your PARTS: section, and there is no existing part named 'Part1'.
--Mark
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I was afraid because milythael said to do not post code here.
But to assemble the chip, I tried two ways:
/* Not gate */
CHIP Not {
IN v;
OUT out;
PARTS:
Part1(..., out=v);
Part2(in=v, ...);
Part3(a=v, b=v);
Nand(a=v, b=v, out=out);
}And:
/* Not gate */
CHIP Not {
IN v;
OUT out;
PARTS:
Part1(in=v, out=v);
Nand(a=v, b=v, out=out);
}And I got the same error on both.
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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It's OK to post code to get help, particularly broken code. You should edit your posts to remove the code after you get help.
The first thing that you want to do is read the first section of The Hardware Construction Survival Kit that describes how to get the stub HDL files and the test files for the hardware projects. It is important to use the same names for the input and output pins as are documented in the book so that the test files will work. The HDL stubs make this easy.
Logically, you're on the right track. All you need to do is to remove the 'Part#' lines. I think that you were confused by an example that was trying to show a generic implementation.
You will also want to change 'v' to 'in' so that the Not.tst file will work correctly.
--Mark
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I got all my first gates, Not, Or, And and Xor, now i'm trying to build the multiplexor. I was thinking and I guess it's not so smart to build it by trial and error, is there something that can help me to build them faster? I also don't want to just see the answers and build them, I want to study something that will allow me to build them faster. I've asked in some forums and they said me something about De Morgan's Law, i'm reading about atm. Any further sugestions?
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Administrator
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Reread 1.1.1 in the book, particularly the paragraph on Canonical Representation. Use the truth table for Mux in Figure 1.8 to determine the canonical representation of Mux. This will result in a functional, but not very elegant, circuit for Mux.
Another way to work out circuits, more artistic than engineering, is to look at the truth table and try to find patterns. For instance with Mux, cover the top half of the truth table and ask "when sel is true, what is out?" then cover the top half and ask "when not sel is true, what is out?" Then think about how you can combine the two answers.
--Mark
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Gustavo, follow Mark's suggestion by creating a "canonical representation" of the Mux function. The circuit you build will match that canonical representation exactly.
It's important to recognize the relationship between Boolean algebraic expressions and circuits... they are, for the most part, exactly the same thing.
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