I have written my HDL implementation which in my head works perfectly but fails in the simulator (comparison line 7 & 8)
Is it because I'm ignoring the fact that it is 16way?
In my head, it works like this.
sell inputs are 00 so the first mux operation will output an
a to
m1the second mux operation will output a
b to
m2the third mux operation will output
m1 which is an
asel inputs are 01so the first mux operation will output an
a to
m1the second mux operation will output a
b to
m2the third mux operation will output
m2 which is an
bsel inputs are 10so the first mux operation will output an
c to
m1the second mux operation will output a
d to
m2the third mux operation will output
m1 which is an
csel inputs are 11so the first mux operation will output an
c to
m1the second mux operation will output a
d to
m2the third mux operation will output
m2 which is an
dI'm really confused because I built it in a logic gate GUI and it works