Comparision failed at Line 5

[amrit239]

I am trying to code And Gate.

Here is the code,

```hdl

<CHIP CODE REMOVED>

```

For (0,0), (0,1) and (1,0) input values, out is 0.
However for (1,1) Nand gate produce w1=1.

What am I doing wrong here?

[code2win]

I want a screenshot of that. Make it good.

[ivant]

Have you implemented the NOT gate?

[amrit239]

CONTENTS DELETED

The author has deleted this message.

[Lozminda]

Hi
It's a while since i did this chapter, so i might be completely wrong, but have you got your connections the right way round? say the output of the Nand gate and input of the Not gate?
Perhaps something to check as well ?
Loz

[amrit239]

The CHIP design is straight forward.

```
<CHIP CODE REMOVED>
```

I also tried by renaming `w1` to `nand`, `nandout` and `w` but still for (1,1) input values, out is 0.

[ivant]

amrit239 wrote

The CHIP design is straight forward.

...

I also tried by renaming `w1` to `nand`, `nandout` and `w` but still for (1,1) input values, out is 0.

I tried this and I can reproduce your error when I haven't implemented the Not gate. When I added the Not implementation, the And tests passed.

You should implement the chips in the order that is described in the book/course.

P.S. After checking that your And gate works, please remove the code from your posts.

[amrit239]

Ok.

I have received two comments saying I should implement Not gate first. I don't know, because I am using it in code assuming that it is already Builtin, but I'll read once more thoroughly to see if I missed implementation part.

For now, I'll remove the code from this thread :)

[ivant]

amrit239 wrote

Ok.

I have received two comments saying I should implement Not gate first. I don't know, because I am using it in code assuming that it is already Builtin, but I'll read once more thoroughly to see if I missed implementation part.

For now, I'll remove the code from this thread :)

Most chips are not implemented and it's important to implement them in the order specified in the book.

[Lozminda]

Section 1.5 says

All the chips should be implemented using the HDL language specified in appendix A

( Perhaps : All the chips should be implemented; using the HDL language specified in appendix A
or
(All the chips should be implemented. Using the HDL language specified in appendix A)

In 'defence' of us students there is a bit of ambiguity in that sentence, because if you go to the appendix, it does go on about builtin chips a lot.

However 'building' all the chips in the right order is what the course wants. It also gets you into the HWSimulator and HDL language format too. I think you can move the built in chips into different directories to get different functionality with the simulator but it was a while since i did this chapter...

[amrit239]

Thanks for all the help.

1. I found that I was using Not gate without implementing it.
2. This can be solved with Nand gate alone.