I'm having a very hard time telling exactly what you are asking or trying to do because you have so many typos in your post. I think I get the main gist, but it's impossible to tell for sure. Please proof read and clean up your posts carefully before you post them (and, of course, mistakes will still sneak through, but it will hopefully be minor enough that it will be fairly easy to infer what was meant).
What gate is it you are trying to implement? I have no idea what you mean by a "nad gatter".
When you say you have:
kiohoilgb8 wrote
CHIP t {
IN a,b;
OUT out;
PARTS:
}
Where is that 't' in the first line coming from?
The name of the gate you are implementing needs to go there.
When you have:
PARTS:
NAND(a=true, b=false)
You are saying that the chip you are making consists of a single Nand gate in which one input is tied permanently HI (true) and the other is tied permanently LO (false), but whose output isn't connected at all. You are also saying that neither of the two chip inputs is connected to anything and neither is the one chip output.
The text gives you an example HDL file for the Xor gate (even though you haven't implemented any of the parts it uses yet, but you can use the built-in parts to get the simulation to run if you want).
Let's make a fictional gate that I'll call a 'Fred' gate. It has three inputs, 'tom', 'sally', and 'mary'. It also has one output, 'henry'.
The logic that we are trying to implement is the following:
tom sally mary henry
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Before we do any of the internal implementation, we can set up the basic HDL file as follows:
CHIP Fred {
IN tom, sally, mary;
OUT henry;
PARTS:
// Put your code here:
}
Do you see how those top three lines define the interface of this part to the rest of the world in terms of the name of the chip and the names of the input and output signals?
Now we can turn our attention to the internal logic.
We know that a Nand gate has the following behavior:
a b out
0 0 1
0 1 1
1 0 1
1 1 0
Notice that if either input is LO (0), the output will be HI (1) regardless of what the other input happens to be.
Next, notice from the truth table for our 'Fred' gate that the output is HI any time that the 'tom' input is LO. That means that we can use a Nand gate to get a good portion of our desired behavior by connecting one input to 'tom' and using the output for the chip's output ('henry'). But the other input to this Nand gate depends on both of the other two chip inputs ('sally' and 'mary'). So we will need some additional logic that uses 'sally' and 'mary' as inputs and produces a new, purely internal signal (which we will call 'danny'). At this point our (still incomplete) implementation looks like this:
CHIP Fred {
IN tom, sally, mary;
OUT henry;
PARTS:
// Need something here to use sally and mary to generate danny
Nand(a = tom, b = danny, out = henry);
}
What does the missing logic need to do? Let's add 'danny' to our truth table and take into account that 'henry' is the Nand of 'tom' and 'danny'.
tom sally mary danny henry
0 0 0 x 1
0 0 1 x 1
0 1 0 x 1
0 1 1 x 1
1 0 0 1 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
When 'tom' is LO, we don't care what 'danny' happens to be (indicated by the 'x' in the truth table) because the Nand gate will force 'henry' to be HI. But when 'tom' is HI, we see that we need 'danny' to be the Nand of 'sally' and 'mary'. Thus our final design becomes:
CHIP Fred {
IN tom, sally, mary;
OUT henry;
PARTS:
Nand(a = sally, b = mary, out = danny);
Nand(a = tom, b = danny, out = henry);
}
Now, what if the pin names for our 'Fred' gate were the more traditional 'a', 'b', and 'c' for the three inputs and 'out' for the output? Simple -- every place where we have 'tom' we replace it with 'a' and so on. We can name purely internal signals anything we want (other than one of the names used for the chip's input and output. The only internal signal we have is 'danny', so let's replace it with 'd'. That would make our logic design:
CHIP Fred {
IN a, b, c;
OUT out;
PARTS:
Nand(a = b, b = c, out = d);
Nand(a = a, b = d, out = out);
}
The fact that our Nand gate has a pin called 'a' and our chip has a signal called 'a' is not an issue. In the pin list for given part, the name on the left of the equals sign is the name of one of that part's pins while the name on the right of the equals sign is the name of one of the signals in the chip's design (either a pin or an internal signal). These are completely separate and distinct things.
Locked
