Mux16 issue

[Jack]

hi, I have a trouble when build  Mux16 chip,  the hdl file content as following,

CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    Not(in=sel, out=w1);
    And16(a=a, b[0..15]=w1, out=w2);
    And16(a=b, b[0..15]=sel, out=w3);
    Or16(a=w2, b=w3, out=out);
}

it show error 'b(16) and w1(1) have different bus widths',  I can't find out the syntax error,
Does anyone help review pls, thanks.

[cadet1620]

The problem here is that b for an And16 is 16 bits wide and w1 is a single bit signal.

To make this work you will need to hook w1 to each individual bit in b:
    And16(a=a, b[0]=w1, b[1]=w1 ... b[15]=w1, out=w2);
and the same for sel.

You might want to make Mux16 out of Mux, similar to how you made And16.

(Note that true and false automatically expand to match bus widths, which is often useful.)

--Mark

[Jack]

understand now, thanks very much.

[Eugeniu]

In order to avoid setting each of the pins of the bus you could create a 'Repeater' (one input, many outputs identical to the input).

[cadet1620]

[edit: 'sel', not 'in']

Mux16 can do this for you:

    Mux16 (sel=signal, a=false, b=true, out=signal16);

--Mark

[Eugeniu]

Totally agree with your solution. Although using a Repeater is more efficient in terms of latency :)

[Max Kennedy]

It's also possible to get one of the gates you previously built wrong, but have it pass the testing - it isn't an exhaustive test as mentioned in the instructions.

If you are sure your logic and syntax is correct, look at what is going into it.