I have now given this question a bit more thought in the clear light of morning. I agree with WBahn about the purpose of the diagram: to illustrate the need to read the output of combinational gates only after time is allowed for a change in input signal to propagate through the gate to the output. The outputs of combinational gates are considered valid and to be used only at a specific, regular point in each clock cycle. Therefore, although combinational circuits do not depend on the clock for their operation, they certainly depend on the clock for their use. This is made much more clear in several slides provided for Project 3 on the From Nand to Tetris web site which I reproduce below (the slides are snipped from the version revised for the 2nd Ed of the book):
![Chapter 3 Slide, 2nd Ed-Slide 17](http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036286/Slide_17.png)
![Chapter 3 Slide, 2nd Ed-Slide 18](http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036286/Slide_18.png)
![Chapter 3 Slide, 2nd Ed-Slide 19](http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036286/Slide_19.png)
My original complaint was that the Not gate in the diagram shows inconsistent response behavior. Only in the questioned section does the output response lag behind the input. In every other case, the input and response occur together. Such unpredictable behavior would seem to me to be undesirable.