Question about Figure 3.2, Page 48, Second Edition of the book

[charleszzx]

When studying Figure 3.2, Page 48, Second Edition of the book, I can't understand one particular part of the diagram circled red. If we probe at the transition between Cycle 3 and 4, input and output signals are both 1. However, since the picture shows a NOT gate, shouldn't the input and output signal have opposite values? Thanks for the help!

[rleininger]

To me, the response of the Not gate presented in Figure 3.2 seems inconsistent.  I would think the transition to logic 1 that occurs during cycle 3 should produce the same response that is shown in cycle 1.  The change would produce a diagram such as shown below.  But I may be missing something.

[charleszzx]

I agree. This is more likely an error in the new edition of the book.

[WBahn]

I think the point of the figure is to show the effect of the propagation delay through the gate. Say the gate has a propagation delay of 10 ns (just making up a number). When the input to the gate changes, the output won't start changing until about 10 ns after the input changes. So during that time both the input and the output will appear to be the same value.

[charleszzx]

If that is the case, does it imply that this particular NOT gate will output the wrong values sometimes?

[WBahn]

If will if you don't give it time to process its inputs.

Things in the real world do not happen instantly. They take time. Your design has to take this into account by ensuring that there is enough time for all signals to propagate from input to output along all paths (the slowest path is known as the critical path and it drives the design). The critical path sets that maximum clock speed in your system. If you run you system faster than that, you risk capturing values that have not settled to their correct states.

[charleszzx]

So can we conclude that the clock speed is not properly designed since we have input=output=1 when we probe the transition between Cycle 3 and 4?

[WBahn]

No. You can't conclude that. ANY time the input to a logic gate changes, it WILL take a finite amount of time before that change is reflected in the inputs.

A basic logic gate doesn't know anything about clock cycles. Changes in the input are reflected at the output once they have propagated through the circuitry in the gate. That takes a certain amount of time.

What is troubling about that diagram isn't that there is a delay, but why/how the input is changing BEFORE the clock edge. The better representation would be to show the input changing at (or shortly after) a clock edge to reflect the fact that the cause for it to start changing is a change in the output of some register, which happens in conjunction with a clock edge. Then show the output changing slightly later, but being finished and stable before the next clock edge.

[rleininger]

I have now given this question a bit more thought in the clear light of morning.  I agree with WBahn about the purpose of the diagram: to illustrate the need to read the output of combinational gates only after time is allowed for a change in input signal to propagate through the gate to the output.  The outputs of combinational gates are considered valid and to be used only at a specific, regular point in each clock cycle.  Therefore, although combinational circuits do not depend on the clock for their operation, they certainly depend on the clock for their use.  This is made much more clear in several slides provided for Project 3 on the From Nand to Tetris web site which I reproduce below (the slides are snipped from the version revised for the 2nd Ed of the book):







My original complaint was that the Not gate in the diagram shows inconsistent response behavior.  Only in the questioned section does the output response lag behind the input.  In every other case, the input and response occur together.  Such unpredictable behavior would seem to me to be undesirable.

[charleszzx]

Thank you so much for the explanation. I did find that part of the diagram a bit confusing. Now I understand it a lot better!

[charleszzx]

These slides are helpful. I am starting to think that maybe it makes more sense to shift all vertical green lines half-cycle to the right. By doing this, we are still probing "at a specific, regular point in each clock cycle". Then, if we probe at these new positions, the values make sense.

[WBahn]

That Slide 18 was poorly thought out.

That they have the input changing slightly before the clock edge in the middle of the slide is annoying, but it's hard to claim it is wrong (the input might be changing because of some external event unrelated to the clock). But the last transition (as well as the transition between 1 & 2) shows the output starting to change before the input has started to change. THAT makes no sense whatsoever (unless the Not gate is psychic).

To be consistent, they need to pick an amount of time (say 10% of a clock cycle) for the delay and then consistently show that the output starts to change that amount of time after the input started to change. A more accurate notion would be that it starts to change one propagation delay after the input changes about half way, but if the transitions are drawn uniformly, this doesn't matter).

[Koki]

The image in this document is incorrect and I believe the image below is correct.